公开(公告)号：US20250133729A1

公开(公告)日：2025-04-24

申请号：US18668696

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Kyusul Park ,  Sungsoo Yim ,  Taeha Suh ,  Hyeonkyu Lee

IPC: H10B12/00

Abstract: A semiconductor memory device includes a conductive line extending in a first direction, channel regions spaced apart from each other in the first direction over the conductive line and each electrically connected to the conductive line, a back gate electrode spaced apart from the conductive line in a third direction and extending in a second direction between first and second channel regions selected from the channel regions, a pair of word lines spaced apart from each other in the first direction and between the second and third channel regions selected from the channel regions, and epitaxial direct contact plugs extending in the third direction between the channel regions and the conductive line and each including a contact surface contacting one of the channel regions, a protruding contact portion at least partially surrounded by the conductive line, and a vertical contact portion between the contact surface and the protruding contact portion.

公开(公告)号：US20230328956A1

公开(公告)日：2023-10-12

申请号：US17936960

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Son ,  Hojoong Kim ,  Youngsin Kim ,  Hyo-Seok Kim ,  Bongsik Choi ,  Taewoong Koo ,  Taeha Suh

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10897

Abstract: A semiconductor device includes a substrate including a first active pattern having first and second source/drain regions of a cell region, a device isolation layer in a trench defining the first active pattern on the cell region, a buffer layer on the cell region, a line structure extends in a third direction, extends from the cell region to a boundary region, and including a first conductive pattern that passes through the buffer layer and contacts the first source/drain region, a bit line on the first conductive pattern, and a first barrier pattern between the bit line and the first conductive pattern, a pair of spacers respectively on both sidewalls of the line structure, a contact on the second source/drain region, a landing pad on the contact, a first abrasive particle between the contact and the landing pad, and a data storage element on the landing pad.