公开(公告)号：US20250169066A1

公开(公告)日：2025-05-22

申请号：US18826334

申请日：2024-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daesun Kim ,  Suklae Kim ,  Cheonbae Kim ,  Youngseok Park ,  Taejin Park ,  Hyunchul Yoon ,  Hyeonkyu Lee ,  Sungsoo Yim ,  Hyungeun Choi

IPC: H10B12/00 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a semiconductor device. The semiconductor device includes: a first connection region, a first memory block region, and a second connection region sequentially arranged; a first peripheral circuit region vertically overlapping with the first memory block region; first memory cells in the first memory block region; a first word line extending into the first and second connection regions by crossing the first memory block region, and electrically connected to the first memory cells; a first sub-word line driver in the first peripheral circuit region; and a first word line signal path electrically connecting the first word line and the first sub-word line driver. The first word line signal path includes at least one first routing contact coupled to the first word line in the first connection region, and at least one second routing contact coupled to the first word line in the second connection region.

公开(公告)号：US20250151260A1

公开(公告)日：2025-05-08

申请号：US18739698

申请日：2024-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyuk Kim ,  Taejin Park ,  Hyeran Lee ,  Sungsoo Yim

IPC: H10B12/00 ,  H01L29/78

Abstract: A semiconductor device includes bit line structures spaced apart from each other in a first direction, and each of the bit line structures extends in a second direction; channels on the bit line structures, wherein the channels are electrically connected to the bit line structures and spaced apart from each other in the first direction; a gate insulation pattern structure on sidewalls of each of the channels; a gate electrode structure including: a first gate electrode on a first sidewall of the gate insulation pattern structure; and a second gate electrode on a second sidewall of the gate insulation pattern structure, wherein the second sidewall faces the first sidewall in the second direction, wherein the second gate electrode is on a third sidewall in the first direction of an end portion of the gate insulation pattern structure, and wherein the second gate electrode contacts the first gate electrode.

公开(公告)号：US20240397701A1

公开(公告)日：2024-11-28

申请号：US18637580

申请日：2024-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Taejin Kim ,  Sungsoo Yim

IPC: H10B12/00

Abstract: A semiconductor device may include a bit line on a substrate, a bonding layer stacked on the bit line, a first conductive connection pattern stacked on the bonding structure layer, so that the bonding layer is vertically between the bit line and the first conductive layer, a channel stacked on the first conductive connection pattern and including a single crystalline semiconductor material, a second conductive connection pattern contacting the bit line and the first conductive connection pattern, a gate electrode on the bit line and being spaced apart from the channel and the first conductive connection pattern, and a capacitor stacked on the channel.

公开(公告)号：US11302698B2

公开(公告)日：2022-04-12

申请号：US16829025

申请日：2020-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Choi ,  Sungsoo Yim ,  Byeongmoo Kang ,  Seongmo Koo ,  Sejin Park ,  Jinwoo Bae

IPC: H01L27/108 ,  H01L49/02

Abstract: A semiconductor device includes a transistor on a semiconductor substrate including a first area and a second area, and having a gate structure and an impurity area, a first interlayer insulating film covering the transistor, and having a contact plug electrically connected to the impurity area, a capacitor including a lower electrode on the first interlayer insulating film in the second area and electrically connected to the contact plug, a dielectric film coating a surface of the lower electrode, and an upper electrode on the dielectric film, and a support layer in contact with an upper side surface of the lower electrode to support the lower electrode, and extending to the first area, in which the support layer has a step between the first area and the second area.

公开(公告)号：US20250133729A1

公开(公告)日：2025-04-24

申请号：US18668696

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Kyusul Park ,  Sungsoo Yim ,  Taeha Suh ,  Hyeonkyu Lee

IPC: H10B12/00

Abstract: A semiconductor memory device includes a conductive line extending in a first direction, channel regions spaced apart from each other in the first direction over the conductive line and each electrically connected to the conductive line, a back gate electrode spaced apart from the conductive line in a third direction and extending in a second direction between first and second channel regions selected from the channel regions, a pair of word lines spaced apart from each other in the first direction and between the second and third channel regions selected from the channel regions, and epitaxial direct contact plugs extending in the third direction between the channel regions and the conductive line and each including a contact surface contacting one of the channel regions, a protruding contact portion at least partially surrounded by the conductive line, and a vertical contact portion between the contact surface and the protruding contact portion.

公开(公告)号：US20250040126A1

公开(公告)日：2025-01-30

申请号：US18670805

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Kim ,  Taejin Park ,  Kyuchang Kang ,  Hyeonkyu Lee ,  Sungsoo Yim

IPC: H10B12/00

Abstract: A semiconductor device includes a lower circuit pattern, a bit line shield structure, a first insulating interlayer, a bit line structure, a first contact plug, a channel and a capacitor. The lower circuit pattern is on a substrate. The bit line shield structure is on the lower circuit pattern. The first insulating interlayer is in an opening extending through the bit line shield structure. The bit line structure is on the bit line shield structure, and at least partially overlaps the bit line shield structure in a vertical direction substantially perpendicular to an upper surface of the substrate. The first contact plug extends through the first insulating interlayer to contact the bit line structure, and is electrically connected to the lower circuit pattern. The channel is on the bit line structure. The capacitor is on the channel and is electrically connected to the channel.

公开(公告)号：US20250167107A1

公开(公告)日：2025-05-22

申请号：US18775049

申请日：2024-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Taejin Park ,  Suklae Kim ,  Cheonbae Kim ,  Sungsoo Yim ,  Yoona Jang ,  Hyunyong Jeong

IPC: H01L23/522 ,  G11C5/06 ,  H01L23/528 ,  H10B12/00

Abstract: A semiconductor device is provided. The semiconductor device includes a first structure having a memory block region and an extension region; and a second structure having a peripheral circuit region. The first structure includes memory cells and a word line. The second structure includes a semiconductor body; a through-insulating pattern in the semiconductor body; and a peripheral transistor. The first and second structures include a word line signal path electrically connecting the word line to the peripheral transistor. The word line signal path includes a word line contact that is in contact with the word line in the extension region; a word line routing lower structure electrically connected to the word line contact and extending from the extension region into the memory block region; and a word line routing connection structure electrically connecting the word line routing lower structure to the word line routing peripheral structure.

公开(公告)号：US11616118B2

公开(公告)日：2023-03-28

申请号：US16938286

申请日：2020-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin Kim ,  Sungsoo Yim ,  Suklae Kim ,  Hyukwoo Kwon ,  Byunghyun Lee ,  Yoonyoung Choi

IPC: H01L49/02 ,  H01L27/108

Abstract: An integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a substrate; and a plurality of supporters having an opening region exposing side surfaces of the plurality of cylindrical structures, the plurality of supporters being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of supporters has both side surfaces having slopes and has a top width that is less than a bottom width.