公开(公告)号：US11367487B2

公开(公告)日：2022-06-21

申请号：US16693925

申请日：2019-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won Park ,  Won Bo Shim ,  Bong Soon Lim

IPC: G11C16/16 ,  G11C16/24 ,  G11C16/34 ,  G11C16/12

Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.

公开(公告)号：US11783900B2

公开(公告)日：2023-10-10

申请号：US17840021

申请日：2022-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won Park ,  Won Bo Shim ,  Bong Soon Lim

IPC: G11C16/16 ,  G11C16/24 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C16/16 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3445

Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.

公开(公告)号：US11200952B2

公开(公告)日：2021-12-14

申请号：US16991821

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Won Park ,  Sang-Wan Nam ,  Ji Yeon Shin ,  Won Bo Shim ,  Jung-Yun Yun ,  Ji Ho Cho ,  Sang Gi Hong

IPC: G11C16/10 ,  H01L25/065 ,  H01L25/18 ,  G11C16/04 ,  H01L23/00

Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.

公开(公告)号：US11322205B2

公开(公告)日：2022-05-03

申请号：US16823275

申请日：2020-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Won Park ,  Sang-Wan Nam ,  Ji Yeon Shin ,  Won Bo Shim ,  Jung-Yun Yun ,  Ji Ho Cho ,  Sang Gi Hong

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.