公开(公告)号：US11176402B2

公开(公告)日：2021-11-16

申请号：US16613627

申请日：2018-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deok-ho Kim ,  Won-woo Lee ,  Jae-woong Lee ,  Bong-hoon Park ,  Gun-Ill Lee ,  Ji-won Jeong ,  Teresa Ka Ki Ng

IPC: G06K9/32 ,  G06K9/62 ,  G06K9/20

Abstract: Provided are an artificial intelligence (AI) system for simulating functions such as recognition, determination, and so forth of the human brain by using a mechanical learning algorithm like deep learning, or the like, and an application thereof. The disclosure relates to a method, performed by a device, of identifying an object, and the method includes obtaining an image including an object, extracting attribute information of the object from the image by using a plurality of layers included in a network for determining a category of the object, obtaining feature information representing the object by combining attribute information extracted from at least some layers among the plurality of layers by using at least one feature extraction layer, and identifying the object based on a result of comparing the obtained feature information with feature information of each of a plurality of previously stored object images, wherein a parameter of each of the at least one feature extraction layer is configured according to a training result based on a database including a plurality of images.

公开(公告)号：US08873277B2

公开(公告)日：2014-10-28

申请号：US13648300

申请日：2012-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeoung-won Seo ,  Soo-ho Shin ,  Won-woo Lee ,  Jeong-soo Park ,  Young-yong Byun ,  Seong-jin Jang ,  Sang-woong Shin

IPC: G11C7/00 ,  G11C11/4091 ,  G11C8/14 ,  G11C11/4094 ,  G11C7/12

CPC classification number: G11C8/14 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract translation: 半导体存储器件包括多个存储单元块，它们包括具有位线的第一存储单元块，边沿读出放大器块，其包括耦合到第一存储单元块的位线的一部分的边沿读出放大器，以及平衡电容器单元 耦合到边缘读出放大器。