公开(公告)号：US20250071980A1

公开(公告)日：2025-02-27

申请号：US18755088

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonyoung JEONG ,  Choonghyun LEE ,  Jooncheol KIM ,  Sunyoung LEE ,  Youngseung CHO

IPC: H10B12/00

Abstract: A semiconductor device may include a substrate including, lower bit line structures from a first region to a second region adjacent to the first region and extending in a second direction perpendicular to the first direction, a second gate structure on the second region of the substrate to be spaced apart from the lower bit line structure, a first offset spacer on a first sidewall corresponding to an end of each of the lower bit line structures in the second direction, a second offset spacer and a first spacer sequentially arranged on a sidewall of the second gate structure, an insulation liner layer at least disposed a surface of the first offset spacer, and a capping pattern covering the lower bit line structures and an upper portion of the second gate structure. The first offset spacer and the insulation liner layer include silicon nitride.