公开(公告)号：US20240179912A1

公开(公告)日：2024-05-30

申请号：US18436169

申请日：2024-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sanghee YOON ,  Wooyong JEON ,  Junyoung CHOI ,  Yoonjo HWANG

IPC: H10B43/27 ,  H10B12/00 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B12/50 ,  H10B43/40

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

公开(公告)号：US20220173119A1

公开(公告)日：2022-06-02

申请号：US17368029

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sanghee YOON ,  Wooyong JEON ,  Junyoung CHOI ,  Yoonjo HWANG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/108

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.