公开(公告)号：US20240341091A1

公开(公告)日：2024-10-10

申请号：US18296389

申请日：2023-04-06

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yun-Feng Kao ,  Wei Lee ,  Jyun-Yan Kuo ,  Katherine H. Chiang

IPC分类号： H10B12/00

CPC分类号： H10B12/50 ,  H10B12/09 ,  H10B12/315

摘要： A semiconductor device includes: an array of memory cells located over a substrate, wherein each of the memory cells includes a respective instance of an access transistor and a respective instance of a memory structure configured to store a data bit and electrically connected to a source structure of the respective instance of the access transistor; and a memory monitor device including an additional instance of the access transistor, an additional instance of the memory structure that is electrically connected to a source structure of the additional instance of the access transistor, and at least one monitor transistor having a respective monitor gate electrode that is electrically connected to the source structure of the additional instance of the access transistor.

公开(公告)号：US20240341081A1

公开(公告)日：2024-10-10

申请号：US18388295

申请日：2023-11-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hongjun LEE ,  Keunnam KIM ,  Seungmuk KIM ,  Kiseok LEE

IPC分类号： H10B12/00 ,  G11C5/06

CPC分类号： H10B12/315 ,  G11C5/063 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

摘要： A semiconductor device which includes a semiconductor substrate having a cell area and a peripheral area, the peripheral area including a first area and a second area adjacent to each other, first transistors on the first area, a first wiring layer on the first transistors, a first pad on the second area and a portion of the first area, a first contact plug between the first wiring layer and the first area, a second contact plug between the first pad and the first area, a second pad on the first wiring layer, a third contact plug between the second pad and the first wiring layer, and a plurality of first capacitors on the second pad and that vertically overlap the first transistors, thus reliability and electrical characteristics of the semiconductor device may be increased.

公开(公告)号：US20240339325A1

公开(公告)日：2024-10-10

申请号：US18749899

申请日：2024-06-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： JAR-MING HO

IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L23/544 ,  H10B12/00

CPC分类号： H01L21/28506 ,  H01L21/3213 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/544 ,  H10B12/00 ,  H10B12/09 ,  H10B12/50

摘要： The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

公开(公告)号：US20240332262A1

公开(公告)日：2024-10-03

申请号：US18740603

申请日：2024-06-12

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Shunpei YAMAZAKI

IPC分类号： H01L25/065 ,  G11C5/06 ,  H01L23/00 ,  H01L29/786 ,  H10B12/00

CPC分类号： H01L25/0657 ,  G11C5/063 ,  H01L29/78693 ,  H10B12/315 ,  H10B12/50 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

摘要： A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

公开(公告)号：US12106796B2

公开(公告)日：2024-10-01

申请号：US17994922

申请日：2022-11-28

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Nozomu Harada ,  Koji Sakui

IPC分类号： G11C5/06 ,  G11C11/409 ,  H10B12/00

CPC分类号： G11C11/409 ,  G11C5/06 ,  H10B12/20 ,  H10B12/50

摘要： An N+ layer 11a and N+ layers 13a to 13d that are disposed on both ends of Si pillars 12a to 12d standing on a substrate 10 in a vertical direction, a TiN layer 18a that surrounds a gate HfO2 layer 17a surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, a TiN layer 18b that surrounds the gate HfO2 layer 17a and that extends between the Si pillars 12c and 12d, a TiN layer 26a that surrounds a gate HfO2 layer 17b surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, and a TiN layer 26b that surrounds the gate HfO2 layer 17b and that extends between the Si pillars 12c and 12d are formed. Voltages applied to the N+ layers 11a and 13a to 13d and the TiN layers 18a, 18b, 26a, and 26b are controlled to perform a data write operation of retaining, inside the Si pillars 12a to 12d, a group of positive holes generated by an impact ionization phenomenon and a data erase operation of discharging the group of positive holes from the inside of the Si pillars 12a to 12d.

公开(公告)号：US20240324178A1

公开(公告)日：2024-09-26

申请号：US18593978

申请日：2024-03-04

申请人： Kioxia Corporation

发明人： Kasumi OKABE ,  Akifumi GAWASE ,  Kazuhiro KATONO ,  Kotaro NODA ,  Takanori AKITA ,  Takahiro FUJII

IPC分类号： H10B12/00

CPC分类号： H10B12/33 ,  H10B12/50

摘要： A semiconductor device includes a first electrode, an oxide semiconductor layer electrically connected to the first electrode and disposed above the first electrode, a gate electrode facing the oxide semiconductor layer with an insulating film interposed therebetween, and a second electrode including a first conductive layer electrically connected to the oxide semiconductor layer and disposed above the oxide semiconductor layer, the first conductive layer containing oxygen, indium, and tin. The second electrode further includes a second conductive layer in contact with the first conductive layer and containing oxygen and a first metal and a third conductive layer in contact with the second conductive layer and containing the first metal.

公开(公告)号：US12100629B2

公开(公告)日：2024-09-24

申请号：US17653219

申请日：2022-03-02

申请人： Micron Technology, Inc.

发明人： Kevin J. Torek

IPC分类号： H01L21/82 ,  H01L21/02 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC分类号： H01L21/823885 ,  H01L21/02565 ,  H01L21/308 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/315 ,  H10B12/50

摘要： A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

公开(公告)号：US12096620B2

公开(公告)日：2024-09-17

申请号：US17451645

申请日：2021-10-20

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Yexiao Yu

IPC分类号： H01L27/108 ,  G11C5/06 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

CPC分类号： H10B12/488 ,  G11C5/063 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76862 ,  H01L23/5283 ,  H01L23/53266 ,  H10B12/50

摘要： A method for manufacturing a memory includes: providing a substrate having a core region provided with a word line; forming a dielectric layer on the substrate, and etching the dielectric layer to form a first filling hole exposing the word line; forming a barrier layer on a hole wall of the first filling hole, where the barrier layer located in the first filling hole surrounds and forms a first intermediate hole exposing the word line; etching the word line exposed in the first intermediate hole to remove a first residue on the word line; and forming in the first intermediate hole a first wire electrically connected to the word line.

公开(公告)号：US20240306381A1

公开(公告)日：2024-09-12

申请号：US18669828

申请日：2024-05-21

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Rongbin LIU ,  Junkeun LEE ,  Sangpil LEE ,  Sangbong HAN ,  Zhengbo WANG

IPC分类号： H10B12/00 ,  G11C11/408 ,  G11C11/4093

CPC分类号： H10B12/50 ,  G11C11/4087 ,  G11C11/4093

摘要： This disclosure relates to storage circuits, memories, and storage apparatuses. An example memory includes a storage circuit. The storage circuit includes a first bank, a second bank, a first global data amplifier, global input/output (GIO) routing, and an interface circuit. The first bank and the second bank share the first global data amplifier, and the first global data amplifier is coupled to the interface circuit through the GIO.

公开(公告)号：US12089396B2

公开(公告)日：2024-09-10

申请号：US17724344

申请日：2022-04-19

申请人： Samsung Electronics Co., Ltd.

发明人： Jongmin Lee

IPC分类号： H01L21/00 ,  H01L49/02 ,  H10B12/00

CPC分类号： H10B12/315 ,  H01L28/92 ,  H10B12/50 ,  H10B12/0335 ,  H10B12/09

摘要： A semiconductor device may include a cell capacitor including first lower electrodes, a first upper support layer pattern, a first dielectric layer, and a first upper electrode. The decoupling capacitor may include second lower electrodes, a second upper support layer pattern, a second dielectric layer, and a second upper electrode. The first and second lower electrodes may be arranged in a honeycomb pattern at each vertex of a hexagon and a center of the hexagon. The first upper support layer pattern may be connected to upper sidewalls of the first lower electrodes. The first upper support layer pattern may correspond to a first plate defining first openings. The second upper support layer pattern may be connected to upper sidewalls of the second electrodes. The second upper support layer pattern may correspond to a second plate defining second openings having a shape different from a shape of the first opening.