公开(公告)号：US11950417B2

公开(公告)日：2024-04-02

申请号：US17172458

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wukang Kim ,  Sejun Park ,  Hyoje Bang ,  Jaeduk Lee ,  Junghoon Lee

IPC: H01L29/423 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11524 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/535 ,  H10B43/35

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

公开(公告)号：US20240206177A1

公开(公告)日：2024-06-20

申请号：US18591076

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wukang Kim ,  Sejun Park ,  Hyoje Bang ,  Jaeduk Lee ,  Junghoon Lee

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/535 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/535 ,  H10B43/35

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

公开(公告)号：US20210408037A1

公开(公告)日：2021-12-30

申请号：US17172458

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wukang Kim ,  Sejun Park ,  Hyoje Bang ,  Jaeduk Lee ,  Junghoon Lee

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/535

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.