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公开(公告)号：US20240365546A1
公开(公告)日：2024-10-31
申请号：US18639781
申请日：2024-04-18
发明人： Ramanathan Gandhi
摘要： Methods, systems, and devices for multiple metal word line gates in a three dimensional (3D) memory array are described. A multi-metal control gate may be formed and used to access the memory cells. The metals may be selected such that an electric field induced in the memory cell during access is relatively even across its area. For example, metals having different work functions or resistivities may induce different electric fields. Accordingly, metals may be selected to increase an electric field induced in a planar region in the memory cell relative to if a single metal control gate were implemented such that relatively even electric fields are induced throughout the memory cell. To support formation of the multi-metal control gate, a portion of the metal forming the control gate may be partially etched and replaced with one or more other metals to form the multi-metal control gate.
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2.发明公开公开(公告)号：US20240357824A1
公开(公告)日：2024-10-24
申请号：US18526285
申请日：2023-12-01
发明人： Byong Ju KIM , Dong Sung CHOI , Won Jun PARK , Dong Hwa LEE , Jae Min JUNG , Chang Heon CHEON
摘要： There is provided a semiconductor memory device having improved reliability. The semiconductor memory device includes a cell substrate, a mold stack including mold insulating layers and gate electrodes, which are alternately stacked on the cell substrate, a semiconductor layer extended in a vertical direction crossing an upper surface of the cell substrate to pass through the mold stack, a blocking insulating pattern between the semiconductor layer and each of the gate electrodes, a charge storage layer including a charge trap portion between the semiconductor layer and the blocking insulating pattern and a first charge blocking portion between the semiconductor layer and each of the mold insulating layers, and a tunnel insulating layer between the semiconductor layer and the charge storage layer, wherein an oxygen concentration of the first charge blocking portion is higher than that of the charge trap portion.
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公开(公告)号：US20240355735A1
公开(公告)日：2024-10-24
申请号：US18419856
申请日：2024-01-23
发明人： Hyemi LEE , Seungyoon Kim , Heesuk Kim , Sangjae Lee , Jaehoon Lee , Juyoung Lim , Minkyu Chung , Sanghun Chun , Jeehoon Han
IPC分类号： H01L23/528 , H01L23/522 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
CPC分类号： H01L23/5283 , H01L23/5226 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2225/06506
摘要： A semiconductor device includes a plate layer, gate electrodes and interlayer insulating layers alternately stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and forming a first stack structure and a second stack structure on the first stack structure, a channel structure penetrating through the gate electrodes and extending in the first direction, and a contact plug extending in the first direction and electrically connected to one of the gate electrodes, wherein the second stack structure includes a first gate electrode on a lowermost portion, a first interlayer insulating layer on the first gate electrode, and a second interlayer insulating layer on the first interlayer insulating layer, and the first interlayer insulating layer has a first thickness, and the second interlayer insulating layer has a second thickness smaller than the first thickness.
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公开(公告)号：US20240347455A1
公开(公告)日：2024-10-17
申请号：US18508757
申请日：2023-11-14
发明人： Jang-gn YUN , Jeehoon HAN , Hyunho KIM
IPC分类号： H01L23/528 , G11C5/06 , H01L25/065 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
CPC分类号： H01L23/5283 , G11C5/063 , H01L25/0652 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2225/0651
摘要： A semiconductor device including a first conductive pattern having a first connection part and a plurality of first branch parts connected to the first connection part, a second conductive pattern having a second connection part and a plurality of second branch parts connected to the second connection part, a first memory channel structure in contact with a corresponding one of the first branch parts and a corresponding one of the second branch parts, and a gate cutting pattern in contact with the corresponding one of the second branch parts and the first connection part may be provided. The first conductive pattern and the second conductive pattern may be spaced apart from each other.
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公开(公告)号：US20240339403A1
公开(公告)日：2024-10-10
申请号：US18405362
申请日：2024-01-05
发明人： Moorym Choi , Taeyong Kim , Sunil Shim , Minhee Lee , Yunsun Jang , Hayoung Jeong
IPC分类号： H01L23/528 , H01L23/522 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
CPC分类号： H01L23/5283 , H01L23/5226 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2225/06506
摘要： A semiconductor device includes a first semiconductor structure including a first substrate, and a lower bonding structure on the first substrate, and a second semiconductor structure including a second substrate, and an upper bonding structure bonded to the lower bonding structure. The second semiconductor structure includes via patterns on the second substrate, a source contact pad including a material different from that of the second substrate, a source contact plug electrically connected to the source contact pad, a source contact via on the source contact pad, and an interconnection line that electrically connects the via patterns to the source contact plug. Lower surfaces of the via patterns are farther from the first substrate than a lower surface of the source contact via, and an upper surface of the second substrate is farther from the first substrate than an upper surface of the source contact pad.
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公开(公告)号：US20240339328A1
公开(公告)日：2024-10-10
申请号：US18296503
申请日：2023-04-06
发明人： Alec Dorfner , Minjoon Park
IPC分类号： H01L21/311 , H01L21/02 , H01L21/033 , H01L21/3105 , H01L21/768
CPC分类号： H01L21/31116 , H01L21/02164 , H01L21/0217 , H01L21/0332 , H01L21/31051 , H01L21/31144 , H01L21/76819 , H01L21/76834 , H01L21/76877 , H01L23/5283 , H01L23/53257 , H10B41/35 , H10B43/35
摘要： A method of processing a substrate that includes: forming a conformal etch stop layer (ESL) over a staircase pattern of the substrate, the staircase pattern including staircases, each of the staircases including a conductive surface; forming a dielectric layer over the ESL; planarizing a top surface of the dielectric layer; forming a patterned hardmask over the dielectric layer; and etching the dielectric layer selectively to the ESL using the patterned hardmask as an etch mask to form a plurality of recesses, each of the plurality of recesses landing on each of the staircases, the ESL protecting the conductive surface from the etching, the etching including exposing the substrate to a plasma generated from a process gas including a fluorocarbon, O2, and WF6, a flow rate of WF6 being between 0.01% and 1% of a total gas flow rate of the process gas.
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公开(公告)号：US20240339139A1
公开(公告)日：2024-10-10
申请号：US18746238
申请日：2024-06-18
申请人： Kioxia Corporation
发明人： Hiroki DATE
IPC分类号： G11C7/22 , G11C16/08 , G11C16/10 , G11C16/28 , G11C16/32 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
CPC分类号： G11C7/22 , G11C16/08 , G11C16/10 , G11C16/28 , G11C16/32 , H10B43/27 , H10B43/35 , H10B43/40 , H10B41/27 , H10B41/35 , H10B41/40
摘要： In a semiconductor memory device, in a write operation performed to a memory cell transistor, a first voltage is applied to a first word line and a second voltage lower than the first voltage is applied to a second word line. When a stop command is received during the write operation, a third voltage lower than the second voltage is applied to the first and second word lines, thereafter a fourth voltage higher than the third voltage is applied to a first selection line, thereon or thereafter a fifth voltage higher than the fourth voltage is applied to the first and second word lines, thereafter a sixth voltage lower than the fourth voltage is applied to the first selection line, and thereafter a seventh voltage is applied to the first and second word lines.
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公开(公告)号：US12114500B2
公开(公告)日：2024-10-08
申请号：US17946837
申请日：2022-09-16
IPC分类号： H01L21/28 , H01L21/311 , H01L21/3213 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B99/00
CPC分类号： H10B43/27 , H01L21/31111 , H01L21/32134 , H01L29/40114 , H01L29/40117 , H10B41/27 , H10B41/35 , H10B43/35 , H10B99/00
摘要： Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.
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公开(公告)号：US12112805B2
公开(公告)日：2024-10-08
申请号：US17889471
申请日：2022-08-17
发明人： Yoshiaki Fukuzumi , Jun Fujiki , Shuji Tanaka , Masanobu Saito
IPC分类号： G11C16/10 , G11C16/04 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： G11C16/10 , G11C16/0483 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a plurality of sets of field-effect transistors with each of the sets of field-effect transistors between the data line and a respective string of series-connected memory cells and having N field-effect transistors that are fabricated to have a respective binary permutation of two threshold voltages of a plurality of possible binary permutations of two threshold voltages having N positions, and N select lines that are each connected to a control gate of a respective field-effect transistor of each of the sets of field-effect transistors.
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公开(公告)号：US20240334705A1
公开(公告)日：2024-10-03
申请号：US18457948
申请日：2023-08-29
申请人： SK hynix Inc.
发明人： Chang Woo KANG , Jin Ho KIM
IPC分类号： H10B43/40 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18 , H10B43/27 , H10B43/35 , H10B80/00
CPC分类号： H10B43/40 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2224/08145 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： A semiconductor device may include a first substrate having a first surface and a second surface which faces opposite the first surface. A stack structure disposed on the first surface of the first substrate and including a plurality of interlayer insulating layers and a plurality of horizontal wiring layers which are alternately stacked and a plurality of channel structures which pass through the plurality of interlayer insulating layers and the plurality of horizontal wiring layers may be provided. A plurality of upper transistors may be disposed on the second surface of the first substrate. A logic structure disposed on the stack structure and including a plurality of lower transistors may be provided.
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