公开(公告)号：US20220320083A1

公开(公告)日：2022-10-06

申请号：US17844807

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： MUNHYEON KIM ,  YOUNGCHAI JUNG ,  MINGYU KIM ,  SEON-BAE KIM ,  YEONHO PARK

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

公开(公告)号：US20230023711A1

公开(公告)日：2023-01-26

申请号：US17733143

申请日：2022-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUBONG CHOI ,  YEONHO PARK ,  JUNMO PARK ,  EUNSIL PARK ,  JUNSEOK LEE ,  JINSEOK LEE ,  WANGSEOP LIM

IPC: H01L27/118 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes: first, second and third active patterns on a logic cell region of a substrate and are spaced apart from each other in a first direction; first and second gate electrodes, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; a first separation pattern provided between the first and second active patterns; a second separation pattern provided between the second and third active patterns; a first gate insulating layer interposed between the first gate electrode and the first active pattern; and a first gate cutting pattern interposed between the first and second gate electrodes, and in contact with a top surface of the first separation pattern. The first separation pattern is wider than the second separation pattern, and the first gate insulating layer extends between the first gate electrode and the first separation pattern, and contacts side and top surfaces of the first separation pattern.