Operation method of memory controller configured to control memory device

    公开(公告)号:US12216912B2

    公开(公告)日:2025-02-04

    申请号:US17885823

    申请日:2022-08-11

    Abstract: Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.

    Memory controller managing strong error information and operating method thereof

    公开(公告)号:US11886293B2

    公开(公告)日:2024-01-30

    申请号:US17839369

    申请日:2022-06-13

    CPC classification number: G06F11/1068 G06F11/076 G06F11/0772

    Abstract: A method of operating a memory controller includes: collecting hard decision information based on data read from memory cells of a monitoring unit using a normal read level; collecting soft decision information based on data read from the monitoring unit using one or more offset read levels that are different from the normal read level; storing first strong error information determined based on the hard decision information and the soft decision information in a memory in the memory controller; and updating second strong error information determined for the monitoring unit in the memory after the first strong error information is stored. The second strong error information is used to correct an error in data read in response to a read request from a host.

Patent Agency Ranking