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公开(公告)号:US11037646B2
公开(公告)日:2021-06-15
申请号:US16357431
申请日:2019-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Minuk Kim , Bohwan Jun , Hong Rak Son , Dong-Min Shin , Kijun Lee
Abstract: An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.
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公开(公告)号:US20250014647A1
公开(公告)日:2025-01-09
申请号:US18408126
申请日:2024-01-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Minuk KIM , Soonyoung Kang , Kwanwoo Noh , Dong-Min Shin
Abstract: A storage device includes a nonvolatile memory device including a plurality of first memory cells coupled to a first wordline and a plurality of second memory cells coupled to a second wordline, the first wordline and the second wordline being adjacent to each other, and a storage controller configured to control the nonvolatile memory device. The storage controller is further configured to encode data to be programmed into the plurality of second memory cells, based on a program state of each of the plurality of first memory cells, and encode the data to be programmed into the second wordline such that a first portion of the data to be written into a first portion of the plurality of second memory cells satisfies a first condition, and a second portion of the data to be written into a second portion of the plurality of second memory cells satisfies a second condition.
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公开(公告)号:US11169874B2
公开(公告)日:2021-11-09
申请号:US16547425
申请日:2019-08-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Min Shin , Hong-Rak Son
Abstract: A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.
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公开(公告)号:US20210184699A1
公开(公告)日:2021-06-17
申请号:US16917101
申请日:2020-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Heeyoul Kwak , Jae Hun Jang , Hong Rak Son , Dong-Min Shin , Geunyeong Yu , Kangseok Lee , Hyunseung Han
Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.
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公开(公告)号:US09583189B2
公开(公告)日:2017-02-28
申请号:US15012881
申请日:2016-02-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Pil-Sang Yoon , Eun-Chu Oh , Jun-Jin Kong , Hong-Rak Son , Dong-Min Shin
CPC classification number: G11C13/0097 , G11C11/5607 , G11C11/5657 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0076 , G11C2013/0085 , G11C2213/72
Abstract: A method of operating a memory device including a plurality of memory cells is provided. The method includes receiving a first write command, determining whether a target memory cell is deteriorated or not, in response to the first write command, and writing the second data by selectively erasing the target memory cell according to a result of the determination and by programming the target memory cell.
Abstract translation: 提供一种操作包括多个存储单元的存储器件的方法。 该方法包括响应于第一写入命令,接收第一写命令,确定目标存储器单元是否恶化,以及根据确定结果选择性地擦除目标存储器单元并通过编程来写入第二数据 目标存储单元。
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公开(公告)号:US11206046B2
公开(公告)日:2021-12-21
申请号:US16823913
申请日:2020-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Min Shin , Min Uk Kim , Young Suk Ra , Tae Hyun Song , Seong Hyeog Choi , Hong Rak Son
Abstract: An operating method of a memory controller is provided. The operating method includes receiving a first read data and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation, and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.
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公开(公告)号:US11184030B2
公开(公告)日:2021-11-23
申请号:US16917101
申请日:2020-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Heeyoul Kwak , Jae Hun Jang , Hong Rak Son , Dong-Min Shin , Geunyeong Yu , Kangseok Lee , Hyunseung Han
Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.
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公开(公告)号:US10693503B2
公开(公告)日:2020-06-23
申请号:US16013053
申请日:2018-06-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Min Shin , Min Uk Kim , Ki Jun Lee , Jun Jin Kong , Hong Rak Son
Abstract: A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.
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公开(公告)号:US12216912B2
公开(公告)日:2025-02-04
申请号:US17885823
申请日:2022-08-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seonghyeog Choi , Dong-Min Shin , Hong Rak Son , Hyeonjong Song , Yeongcheol Jo
Abstract: Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.
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公开(公告)号:US11791846B2
公开(公告)日:2023-10-17
申请号:US17314768
申请日:2021-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jae Hun Jang , Dong-Min Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Se Jin Lim
CPC classification number: H03M13/37 , G06F11/085 , G06F11/1012 , G06F13/1673 , H03M13/03
Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
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