公开(公告)号：US20130071976A1

公开(公告)日：2013-03-21

申请号：US13679420

申请日：2012-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsik JEONG ,  Jeonguk HAN ,  Weonho PARK ,  Byungsup SHIM

IPC: H01L21/8239

CPC classification number: H01L21/8239 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

Abstract: Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns.

Abstract translation: 提供了非易失性存储器件及其形成方法，非易失性存储器件可以包括沿着第一方向延伸并且沿与第一方向交叉的第二方向交替地设置在半导体衬底中的第一区域和第二区域。 埋设的掺杂线分别形成在第一区域并沿第一方向延伸。 掩埋掺杂线可以掺杂有第一导电类型的掺杂剂。 掺杂有第二导电类型的掺杂剂的器件区域和器件隔离图案沿第二方向设置。 块区域和器件隔离图案可以形成在第二区域中。 跨越掩埋掺杂线和体区的字线彼此平行地形成。 接触结构连接到掩埋掺杂线并且设置在器件隔离图案之间。

公开(公告)号：US20210013206A1

公开(公告)日：2021-01-14

申请号：US17038435

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： HeonJong SHIN ,  Sunghun JUNG ,  Minchan GWAK ,  Yongsik JEONG ,  Sangwon JEE ,  Sora YOU ,  Doohyun LEE

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/522 ,  H01L29/417

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

公开(公告)号：US20220149043A1

公开(公告)日：2022-05-12

申请号：US17582357

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heonjong SHIN ,  Sunghun JUNG ,  Minchan GWAK ,  Yongsik JEONG ,  Sangwon JEE ,  Sora YOU ,  Doohyun LEE

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/522 ,  H01L29/417

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

公开(公告)号：US20200075595A1

公开(公告)日：2020-03-05

申请号：US16391757

申请日：2019-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heonjong SHIN ,  Sunghun JUNG ,  Minchan GWAK ,  Yongsik JEONG ,  Sangwon JEE ,  Sora YOU ,  Doohyun LEE

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/522 ,  H01L29/417

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.