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    APPARATUS AND METHOD FOR CONTROLLING MEMORY CLOCK FREQUENCY IN WIRELESS COMMUNICATION SYSTEM
    4.
    发明申请
    APPARATUS AND METHOD FOR CONTROLLING MEMORY CLOCK FREQUENCY IN WIRELESS COMMUNICATION SYSTEM 有权
    用于控制无线通信系统中的存储时钟频率的装置和方法

    公开(公告)号：US20130229994A1

    公开(公告)日：2013-09-05

    申请号：US13777224

    申请日：2013-02-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Yong KIM ,  Young-Seok KIM

    IPC: H04W72/08

    CPC classification number: H04W72/082 ,  G06F1/08

    Abstract: The present invention prevents performance degradation caused by a multiplication frequency of a memory clock in a wireless communication system by changing a frequency of the memory clock so that a multiplication frequency is not sufficiently close to a transmission/reception frequency that will cause noise or interference with a data transmission/reception. A communication apparatus according to the present invention includes a controller comprising at least one processor; and a memory for operating at a clock provided from the controller. The controller checks a communication frequency, determines whether the communication frequency is a value in a range of interference from a multiplication frequency of a memory clock frequency, and changes the memory clock frequency.

    Abstract translation: 本发明通过改变存储器时钟的频率来防止由无线通信系统中的存储器时钟的乘法频率引起的性能下降，使得乘法频率不足够接近将导致噪声或干扰的发送/接收频率 数据发送/接收。 根据本发明的通信装置包括：控制器，包括至少一个处理器; 以及用于在从控制器提供的时钟下操作的存储器。 控制器检查通信频率，确定通信频率是否是来自存储器时钟频率的乘法频率的干扰范围内的值，并改变存储器时钟频率。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20160148937A1

    公开(公告)日：2016-05-26

    申请号：US15009948

    申请日：2016-01-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoon PARK ,  Young-Seok KIM ,  Yeong-Cheol LEE

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10888

    Abstract: A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a metal layer pattern on the polysilicon layer pattern, a first spacer surrounding and contacting a sidewall of the bit line structure, the first spacer having a constant thickness, and a capacitor contact structure on the substrate, an air gap being defined between the capacitor contact structure and the first spacer.

    Abstract translation: 半导体器件包括衬底上的位线结构，位线结构具有掺杂杂质的多晶硅层图案，多晶硅层图案上的金属层图案，围绕并接触位线结构侧壁的第一间隔物， 所述第一间隔物具有恒定的厚度，以及所述衬底上的电容器接触结构，气隙限定在所述电容器接触结构和所述第一间隔物之间​​。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150179651A1

    公开(公告)日：2015-06-25

    申请号：US14475687

    申请日：2014-09-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoon PARK ,  Young-Seok KIM ,  Yeong-Cheol LEE

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10888

    Abstract: A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a metal layer pattern on the polysilicon layer pattern, a first spacer surrounding and contacting a sidewall of the bit line structure, the first spacer having a constant thickness, and a capacitor contact structure on the substrate, an air gap being defined between the capacitor contact structure and the first spacer.

    Abstract translation: 半导体器件包括在衬底上的位线结构，位线结构具有掺杂有杂质的多晶硅层图案和多晶硅层图案上的金属层图案，围绕并接触位线结构的侧壁的第一间隔件， 所述第一间隔物具有恒定的厚度，以及所述衬底上的电容器接触结构，气隙限定在所述电容器接触结构和所述第一间隔物之间​​。

    METHOD AND DEVICE WITH CLASSIFICATION VERIFICATION
    9.
    发明申请
    METHOD AND DEVICE WITH CLASSIFICATION VERIFICATION 有权

    公开(公告)号：US20210406688A1

    公开(公告)日：2021-12-30

    申请号：US17469590

    申请日：2021-09-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongmin OK ,  Young-Seok KIM ,  Hwidong NA ,  Sanghyun YOO ,  Hoshik LEE ,  Junhwi CHOI

    IPC: G06N3/08 ,  G06N3/04 ,  G06K9/62

    Abstract: A method and computing device with classification verification is provided. A processor-implemented method includes implementing a classification neural network to generate a classification result of data input to the classification neural network by generating, with respect to the input data, intermediate hidden values of one or more hidden layers of the classification neural network, generating the classification result of the input data based on the generated intermediate hidden values, and generating a determination of a reliability of the classification result by implementing a verification neural network, input the intermediate hidden values, to generate the determination of the reliability.

    RESPONSE INFERENCE METHOD AND APPARATUS
    10.
    发明申请
    RESPONSE INFERENCE METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20200057947A1

    公开(公告)日：2020-02-20

    申请号：US16266395

    申请日：2019-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jehun JEON ,  Young-Seok KIM ,  Jeong-hoon PARK ,  Junhwi CHOI

    IPC: G06N5/04 ,  G06N3/02

    Abstract: Disclosed is a response inference method and apparatus. The response inference apparatus obtains an input, generates a latent variable vector in a latent variable region space partitioned into regions corresponding to a plurality of responses by encoding the input, and generates an output response corresponding to a region from among the regions of the latent variable vector by decoding the latent variable vector.

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