公开(公告)号：US20130229994A1

公开(公告)日：2013-09-05

申请号：US13777224

申请日：2013-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Yong KIM ,  Young-Seok KIM

IPC: H04W72/08

CPC classification number: H04W72/082 ,  G06F1/08

Abstract: The present invention prevents performance degradation caused by a multiplication frequency of a memory clock in a wireless communication system by changing a frequency of the memory clock so that a multiplication frequency is not sufficiently close to a transmission/reception frequency that will cause noise or interference with a data transmission/reception. A communication apparatus according to the present invention includes a controller comprising at least one processor; and a memory for operating at a clock provided from the controller. The controller checks a communication frequency, determines whether the communication frequency is a value in a range of interference from a multiplication frequency of a memory clock frequency, and changes the memory clock frequency.

Abstract translation: 本发明通过改变存储器时钟的频率来防止由无线通信系统中的存储器时钟的乘法频率引起的性能下降，使得乘法频率不足够接近将导致噪声或干扰的发送/接收频率 数据发送/接收。 根据本发明的通信装置包括：控制器，包括至少一个处理器; 以及用于在从控制器提供的时钟下操作的存储器。 控制器检查通信频率，确定通信频率是否是来自存储器时钟频率的乘法频率的干扰范围内的值，并改变存储器时钟频率。

公开(公告)号：US20150325580A1

公开(公告)日：2015-11-12

申请号：US14746205

申请日：2015-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Hun LEE ,  Ki-Yong KIM ,  Sung-Wook PARK ,  Gyu-Yeol LEE

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/823437 ,  H01L21/823443 ,  H01L21/823456 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/788

Abstract: In a semiconductor device, a first gate structure is provided in a cell transistor region and includes a floating gate electrode, a first dielectric layer pattern, and a control gate electrode including a first metal silicide pattern. A second gate structure is provided in a selecting transistor region and includes a first conductive layer pattern, a second dielectric layer pattern, and a first gate electrode including a second metal silicide pattern. A third gate structure is provided in a peripheral circuit region and includes a second conductive layer pattern, a third dielectric layer pattern including opening portions on the second conductive layer pattern, and a second gate electrode including a concavo-convex portion at an upper surface portion thereof and a third metal silicide pattern. The third metal silicide pattern has a uniform thickness.

Abstract translation: 在半导体器件中，第一栅极结构设置在单元晶体管区域中，并且包括浮置栅电极，第一介电层图案和包括第一金属硅化物图案的控制栅电极。 第二栅极结构设置在选择晶体管区域中，并且包括第一导电层图案，第二介电层图案和包括第二金属硅化物图案的第一栅电极。 第三栅极结构设置在外围电路区域中，并且包括第二导电层图案，在第二导电层图案上包括开口部分的第三介电层图案，以及在上表面部分包括凹凸部分的第二栅电极 和第三金属硅化物图案。 第三金属硅化物图案具有均匀的厚度。