APPARATUS AND METHOD FOR GENERATING ASSERTION BASED ON USER PROGRAM CODE, AND APPARATUS AND METHOD FOR VERIFYING PROCESSOR USING ASSERTION
    1.
    发明申请
    APPARATUS AND METHOD FOR GENERATING ASSERTION BASED ON USER PROGRAM CODE, AND APPARATUS AND METHOD FOR VERIFYING PROCESSOR USING ASSERTION 有权
    用于根据用户程序代码生成鉴定的装置和方法,以及使用鉴定验证处理器的装置和方法

    公开(公告)号:US20140075421A1

    公开(公告)日:2014-03-13

    申请号:US14021134

    申请日:2013-09-09

    CPC classification number: G06F8/43 G06F8/41 G06F17/5022 G06F17/5031 G06F17/504

    Abstract: Exemplary embodiments disclose a method for generating an assertion based on a user program code. The method may include receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor, and generating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive.

    Abstract translation: 示例性实施例公开了一种用于基于用户程序代码生成断言的方法。 该方法可以包括接收包括至少一个断言指令,用户程序的编译结果和处理器的体系结构信息的用户程序,并且基于用户程序的编译结果和处理器的体系结构信息, 断言,其声明处理器需要根据由至少一个断言指令中的每一个所指示的用户程序的代码执行的操作。

    VLIW INTERFACE DEVICE AND METHOD FOR CONTROLLING THE SAME

    公开(公告)号:US20170147351A1

    公开(公告)日:2017-05-25

    申请号:US15360271

    申请日:2016-11-23

    Abstract: A VLIW (Very Long Instruction Word) interface device includes a memory configured to store instructions and data, and a processor configured to process the instructions and the data, wherein the processor includes an instruction fetcher configured to output an instruction fetch request to load the instruction from the memory, a decoder configured to decode the instruction loaded on the instruction fetcher, an arithmetic logic unit (ALU) configured to perform an operation function if the decoded instruction is an operation instruction, a memory interface scheduler configured to schedule the instruction fetch request or a data fetch request that is input from the arithmetic logic unit, and a memory operator configured to perform a memory access operation in accordance with the scheduled instruction fetch request or data fetch request.

    METHOD OF COMPRESSING AND RESTORING CONFIGURATION DATA
    4.
    发明申请
    METHOD OF COMPRESSING AND RESTORING CONFIGURATION DATA 有权
    压缩和恢复配置数据的方法

    公开(公告)号:US20150280740A1

    公开(公告)日:2015-10-01

    申请号:US14671377

    申请日:2015-03-27

    CPC classification number: H03M7/60 H03M7/30

    Abstract: A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data used at two or more cycles and generating a bit table indicating valid operations at each of the two or more cycles among operations included in the combined data

    Abstract translation: 一种压缩在可重构处理器中使用的配置数据的方法,包括通过组合在两个或多个周期中使用的配置数据来生成一个组合数据,并且生成指示在组合中包括的操作中的两个或更多个周期中的每一个的有效操作的位表 数据

Patent Agency Ranking