公开(公告)号：US20170017610A1

公开(公告)日：2017-01-19

申请号：US15039603

申请日：2014-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-kwan SUH ,  Suk-jin KIM ,  Chul-soo PARK

IPC: G06F15/78 ,  G06F15/82

CPC classification number: G06F15/7871 ,  G06F1/3225 ,  G06F15/82

Abstract: A technology for controlling a reconfigurable processor is provided. A determination is made as to whether configuration information is provided from a configuration buffer in a preset process performed by the reconfigurable processor, based on address values of the configuration information that are stored in the configuration buffer. Therefore, access to a configuration memory is controlled to reduce power consumption.

Abstract translation: 提供了一种用于控制可重构处理器的技术。 根据存储在配置缓冲器中的配置信息的地址值，确定在由可重配置处理器执行的预设处理中是否从配置缓冲器提供配置信息。 因此，控制对配置存储器的访问以降低功耗。

公开(公告)号：US20160335185A1

公开(公告)日：2016-11-17

申请号：US15107255

申请日：2014-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok KWON ,  Chul-soo PARK ,  Suk-jin KIM

IPC: G06F12/0846 ,  G06F12/0815 ,  G06F12/0886

CPC classification number: G06F12/0851 ,  G06F12/0207 ,  G06F12/0815 ,  G06F12/0886 ,  G06F2212/621 ,  Y02D10/13

Abstract: A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2D) data, and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width.

Abstract translation: 存储器管理方法包括通过参考二维（2D）数据的大小来确定步幅访问的步幅值，并且将2D数据的垂直方向上的相邻数据分配给彼此不同的多个存储体 到确定的步幅值。 因此，可以通过使用具有大数据宽度的存储器来有效地访问垂直方向上的数据。

公开(公告)号：US20170147351A1

公开(公告)日：2017-05-25

申请号：US15360271

申请日：2016-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-chul CHO ,  Suk-jin KIM ,  Chul-soo PARK ,  Dong-kwan SUH

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/78

Abstract: A VLIW (Very Long Instruction Word) interface device includes a memory configured to store instructions and data, and a processor configured to process the instructions and the data, wherein the processor includes an instruction fetcher configured to output an instruction fetch request to load the instruction from the memory, a decoder configured to decode the instruction loaded on the instruction fetcher, an arithmetic logic unit (ALU) configured to perform an operation function if the decoded instruction is an operation instruction, a memory interface scheduler configured to schedule the instruction fetch request or a data fetch request that is input from the arithmetic logic unit, and a memory operator configured to perform a memory access operation in accordance with the scheduled instruction fetch request or data fetch request.