公开(公告)号：US20170084710A1

公开(公告)日：2017-03-23

申请号：US15185253

申请日：2016-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-ho Koh ,  Byoung-ho Kwon ,  Yang-hee Lee ,  Young-kuk Kim ,  In-seak Hwang ,  Bo-un Yoon

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/105 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L21/823475 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897

Abstract: A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.

公开(公告)号：US10109529B2

公开(公告)日：2018-10-23

申请号：US15185253

申请日：2016-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-ho Koh ,  Byoung-ho Kwon ,  Yang-hee Lee ,  Young-kuk Kim ,  In-seak Hwang ,  Bo-un Yoon

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/108

Abstract: A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.