公开(公告)号：US20240292598A1

公开(公告)日：2024-08-29

申请号：US18530748

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suncheul KIM ,  Taeyeon KWON ,  Younjae CHO ,  Jihoon KIM ,  Hongsung MOON

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor memory device may include active regions defined on a substrate by a device isolation layer, each of the active regions including a first impurity region and a second impurity region, word lines on the active regions and extended in a first direction, capping insulating patterns covering top surfaces of the word lines, respectively, bit lines on the word lines and extended in a second direction crossing the first direction, contact plugs between the bit lines and connected to the second impurity region, and data storages on the contact plugs, respectively. Each of the word lines may include a first metal nitride layer and a second metal nitride layer on the first metal nitride layer. A resistivity of the second metal nitride layer may be smaller than a resistivity of the first metal nitride layer.