公开(公告)号：US10304781B2

公开(公告)日：2019-05-28

申请号：US15459917

申请日：2017-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-gyu Baek ,  Yun-rae Cho ,  Hyung-gil Baek ,  Sun-dae Kim

IPC: H01L23/58 ,  H01L23/00 ,  H01L21/66

Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.

公开(公告)号：US20170317035A1

公开(公告)日：2017-11-02

申请号：US15448215

申请日：2017-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-dae Kim ,  Hyung-gil Baek ,  Yun-rae Cho ,  Nam-gyu Baek

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/58 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/585 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.

公开(公告)号：US10103109B2

公开(公告)日：2018-10-16

申请号：US15448215

申请日：2017-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-dae Kim ,  Hyung-gil Baek ,  Yun-rae Cho ,  Nam-gyu Baek

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/78

Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.

公开(公告)号：US20170345773A1

公开(公告)日：2017-11-30

申请号：US15459917

申请日：2017-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-gyu BAEK ,  Yun-rae Cho ,  Hyung-gil Baek ,  Sun-dae Kim

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/66

CPC classification number: H01L23/562 ,  H01L22/34 ,  H01L23/585

Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.