公开(公告)号：US4710893A

公开(公告)日：1987-12-01

申请号：US623381

申请日：1984-06-22

Applicant: Samuel McCutcheon ,  Jeffrey Lum ,  Roman Solek ,  Troy Harrell ,  Robert Leman

Inventor： Samuel McCutcheon ,  Jeffrey Lum ,  Roman Solek ,  Troy Harrell ,  Robert Leman

IPC: G06F13/42 ,  G06F13/00

CPC classification number: G06F13/4213

Abstract: A high speed bus structure and data transfer method to provide data transfer capability between a central processing device and a plurality of electrical modules coupled to the bus. In the preferred embodiment, a central processing unit is coupled to a plurality of electrical modules for data reception and transmission. In a module "listen" cycle, the central processor (CP) device generates a function code which is transmitted on a command bus coupled to each electrical module. The CP device asserts data required by the particular module function on the data bus coupled to each electrical module. The CP device transmits an enable signal (ES) on an enable bus to enable the particular electrical module which is to receive data and asserts a clock signal on a clock line coupled to each module. The enabled electrical module receives valid data from the CP device upon sensing a deasserted clock line denoting the end of a clock cycle. In a module "talk" cycle, an enabled electrical module transmits data to the CP device after transmitting a service request (SRQ) signal to the awaiting CP device which has previously requested a data transmission. Upon receiving the SRQ signal, the CP device asserts an appropriate function code and clock signal. The transmitting module provides its data on the data bus which is received by the CP device as valid data once the clock line is deasserted. Other features include independent module to module communication and a power up bus poll routine for module-slot identification.

Abstract translation: 一种高速总线结构和数据传输方法，用于在中央处理设备和耦合到总线的多个电气模块之间提供数据传输能力。 在优选实施例中，中央处理单元耦合到多个用于数据接收和传输的电气模块。 在模块“监听”周期中，中央处理器（CP）设备产生功能码，该功能码在耦合到每个电气模块的命令总线上传输。 CP设备在耦合到每个电气模块的数据总线上断言特定模块功能所需的数据。 CP设备在使能总线上发送使能信号（ES），以使得能够接收数据的特定电气模块并且在耦合到每个模块的时钟线上断言时钟信号。 启用的电气模块在感测到表示时钟周期结束的无效时钟线时，从CP设备接收有效数据。 在模块“通话”周期中，启用的电气模块在向先前请求数据传输的等待CP设备发送业务请求（SRQ）信号之后向CP设备发送数据。 在接收到SRQ信号时，CP设备断言适当的功能码和时钟信号。 一旦时钟线被断言，发送模块将其数据总线上的数据提供给CP设备作为有效数据。 其他功能包括独立的模块到模块通信和用于模块插槽识别的上电总线轮询程序。

公开(公告)号：US4887051A

公开(公告)日：1989-12-12

申请号：US299398

申请日：1989-01-23

Applicant: Samuel McCutcheon

Inventor： Samuel McCutcheon

IPC: H03K3/03 ,  H03L1/02

CPC classification number: H03K3/03 ,  H03L1/021 ,  Y10S331/03

Abstract: A low phase jitter oscillator which is adjustable in frequency is disclosed. The oscillator comprises a logical OR gate having a feedback loop adjustable in length between the inverted output of the gate and the input of the gate. Using this configuration, the output changes state once every 1/2 T seconds wherein 1/2 T is equal to the propagation delay through the feedback loop and the OR gate. The frequency of the oscillator can be adjusted by adjusting the length of the feedback loop which correspondingly modifies the propagation delay through the feedback loop and thus the frequency of the oscillator output.

Abstract translation: 公开了一种频率可调的低相位抖动振荡器。 该振荡器包括逻辑“或”门，其具有可在栅极的反相输出和栅极输入之间长度可调的反馈回路。 使用这种配置，输出每1/2 T秒改变一次，其中1/2 T等于通过反馈回路和OR门的传播延迟。 振荡器的频率可以通过调整反馈回路的长度进行调整，反馈回路相应地修改通过反馈回路的传播延迟，从而改变振荡器输出的频率。