公开(公告)号：US08325544B2

公开(公告)日：2012-12-04

申请号：US12702809

申请日：2010-02-09

申请人： Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

发明人： Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.

摘要翻译： 提供了包括多个输出缓冲器，选通控制单元和多个选通缓冲器的同步动态随机存取存储器（DRAM）半导体器件。 每个输出缓冲器都配置为输出一位数据。 选通控制单元被配置为响应于外部输入信号输出多个选通控制信号。 选通缓冲器连接到输出缓冲器和选通控制单元，并且每个选通缓冲器被配置为输出至少一个选通信号。 至少一些选通缓冲器响应于选通控制信号被激活，并且输出缓冲器响应于被激活的选通缓冲器输出的选通信号被激活。

公开(公告)号：US20110007576A1

公开(公告)日：2011-01-13

申请号：US12702809

申请日：2010-02-09

申请人： Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

发明人： Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.

摘要翻译： 提供了包括多个输出缓冲器，选通控制单元和多个选通缓冲器的同步动态随机存取存储器（DRAM）半导体器件。 每个输出缓冲器都配置为输出一位数据。 选通控制单元被配置为响应于外部输入信号输出多个选通控制信号。 选通缓冲器连接到输出缓冲器和选通控制单元，并且每个选通缓冲器被配置为输出至少一个选通信号。 至少一些选通缓冲器响应于选通控制信号被激活，并且输出缓冲器响应于被激活的选通缓冲器输出的选通信号被激活。