公开(公告)号：US20130332763A1

公开(公告)日：2013-12-12

申请号：US13493081

申请日：2012-06-11

申请人： Sathappan Palaniappan ,  Romeshkumar Mehta ,  Dharmesh Tirthdasani

发明人： Sathappan Palaniappan ,  Romeshkumar Mehta ,  Dharmesh Tirthdasani

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G11C5/148 ,  Y02D10/14

摘要： A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.

摘要翻译： 存储器件包括一个或多个电源门和状态信号电路。 一个或多个功率门中的每一个都是可配置的，使得存储器件的相应部分被断电。 状态信号电路可操作以产生指示何时配置一个或多个电源门以使得存储器件完全通电的电源状态输出信号。

公开(公告)号：US08947966B2

公开(公告)日：2015-02-03

申请号：US13493081

申请日：2012-06-11

申请人： Sathappan Palaniappan ,  Romeshkumar Mehta ,  Dharmesh Tirthdasani

发明人： Sathappan Palaniappan ,  Romeshkumar Mehta ,  Dharmesh Tirthdasani

IPC分类号： G11C5/14

CPC分类号： G06F1/3275 ,  G11C5/148 ,  Y02D10/14

摘要： A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.

摘要翻译： 存储器件包括一个或多个电源门和状态信号电路。 一个或多个功率门中的每一个都是可配置的，使得存储器件的相应部分被断电。 状态信号电路可操作以产生指示何时配置一个或多个电源门以使得存储器件完全通电的电源状态输出信号。