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公开(公告)号：US07360076B2
公开(公告)日：2008-04-15
申请号：US10144332
申请日：2002-05-13
CPC分类号： G06F21/72 , H04L9/0643 , H04L63/0272 , H04L63/0428 , H04L63/0485 , H04L63/12 , H04L63/164 , H04L63/166 , H04L2209/125 , H04L2209/20 , H04L2209/38
摘要： A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.
摘要翻译： 密码处理系统包括密码电路和散列电路。 输入控制单元和输出控制单元一起工作以流水线方式处理数据分组，其中数据分组在单程中移动通过处理系统。 输入控制单元管理从读取接口接收的数据以及密码电路中的数据的密码处理的开始。 输出控制单元管理输出到写入接口的数据和散列电路中的数据的散列处理。 数据以清晰的数据和密码数据形式移动通过密码电路，使得输出控制单元可以选择性地向散列电路和输出FIFO存储器缓冲器发送清除数据和/或密码数据，输出FIFO存储缓冲器处理在 输出控制单元在将完整处理的数据发送到写入接口之前。
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公开(公告)号：US07266703B2
公开(公告)日：2007-09-04
申请号：US10144004
申请日：2002-05-13
CPC分类号： H04L9/0643 , G06F21/72 , H04L2209/125 , H04L2209/20 , H04L2209/38
摘要： A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.
摘要翻译： 密码处理系统包括密码电路和散列电路。 输入控制单元和输出控制单元一起工作以流水线方式处理数据分组，其中数据分组在单程中移动通过处理系统。 输入控制单元管理从读取接口接收的数据以及密码电路中的数据的密码处理的开始。 输出控制单元管理输出到写入接口的数据和散列电路中的数据的散列处理。 数据以清晰的数据和密码数据形式移动通过密码电路，使得输出控制单元可以选择性地向散列电路和输出FIFO存储器缓冲器发送清除数据和/或密码数据，该缓冲器处理在 输出控制单元在将完整处理的数据发送到写入接口之前。
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公开(公告)号：US06990199B2
公开(公告)日：2006-01-24
申请号：US09978742
申请日：2001-10-16
申请人： James Darren Parker , Satish Anand
发明人： James Darren Parker , Satish Anand
CPC分类号： H04L9/065 , H04L2209/125
摘要： An encryption processing system implements an encryption algorithm using a memory system comprising a multiple-port memory by performing at least one set of parallel read and write operations to the memory. The algorithm is, for example, the conventional ARCFOUR (or RC4) algorithm, and the key and state array used in the ARCFOUR algorithm are stored in the multiple port memory. During execution of the ARCFOUR algorithm, a read from one port of the multiple port memory of a state array value is done while another port is used to write a new value to the state array. The use of such parallel read and write operations uses a comparator system that determines whether to use certain previously-read values from the state array or to read a new value from the state array when selecting the pseudorandom K byte to calculate the output data byte.
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