公开(公告)号：US20130263067A1

公开(公告)日：2013-10-03

申请号：US13626878

申请日：2012-09-25

申请人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了通过接收定制集成电路的规范来自动设计定制集成电路的系统和方法，包括计算机可读代码和定制集成电路上的一个或多个约束; 自动生成具有可编程处理器的计算机体系结构和用于最适合约束的计算机可读代码的一个或多个协处理器; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

公开(公告)号：US08225247B2

公开(公告)日：2012-07-17

申请号：US12835603

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5022

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit.

摘要翻译： 公开了系统和方法以自动设计定制集成电路，包括接收定制集成电路的规范，包括计算机可读代码和定制集成电路上的一个或多个约束; 自动设计处理器架构并且生成独特地定制为满足约束的计算机可读代码的处理器芯片规范; 并将芯片规格合成为定制集成电路的布局。

公开(公告)号：US20120017185A1

公开(公告)日：2012-01-19

申请号：US12835603

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5022

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit.

摘要翻译： 公开了系统和方法以自动设计定制集成电路，包括接收定制集成电路的规范，包括计算机可读代码和定制集成电路上的一个或多个约束; 自动设计处理器架构并且生成独特地定制为满足约束的计算机可读代码的处理器芯片规范; 并将芯片规格合成为定制集成电路的布局。

公开(公告)号：US20120017187A1

公开(公告)日：2012-01-19

申请号：US12835621

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法，以基于算法过程或代码作为输入自动设计定制集成电路，并且使用几乎不需要人为参与的高度自动化的工具。 该方法包括接收包括计算机可读代码和定制集成电路上的一个或多个约束的定制集成电路的规范; 自动生成最适合约束的计算机可读代码的计算机体系结构; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 连续评估和优化一个或多个因素，包括物理实现，以及在RTL或门级合成之上的架构级别的本地和全局区域，时序或功率; 自动生成软件开发工具包（SDK）和相关固件，以执行定制集成电路上的计算机可读代码; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

公开(公告)号：US08370784B2

公开(公告)日：2013-02-05

申请号：US12835621

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法，以基于算法过程或代码作为输入自动设计定制集成电路，并且使用几乎不需要人为参与的高度自动化的工具。 该方法包括接收包括计算机可读代码和定制集成电路上的一个或多个约束的定制集成电路的规范; 自动生成最适合约束的计算机可读代码的计算机体系结构; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 连续评估和优化一个或多个因素，包括物理实现，以及在RTL或门级合成之上的架构级别的本地和全局区域，时序或功率; 自动生成软件开发工具包（SDK）和相关固件，以执行定制集成电路上的计算机可读代码; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。