公开(公告)号：US20110165823A1

公开(公告)日：2011-07-07

申请号：US12748109

申请日：2010-03-26

申请人： Satoru IDE ,  Moriyuki Kashiwa ,  Kazuo Kobayashi ,  Noriyuki Motimaru ,  Eiichi Yamamoto ,  Tomio Kubo ,  Hiroaki Kida

发明人： Satoru IDE ,  Moriyuki Kashiwa ,  Kazuo Kobayashi ,  Noriyuki Motimaru ,  Eiichi Yamamoto ,  Tomio Kubo ,  Hiroaki Kida

IPC分类号： B24B1/00 ,  B24B41/00 ,  B24B7/10

CPC分类号： B24B37/00

摘要： A planarization apparatus and method that thins and planarizes a substrate by grinding and polishing the rear surface of the substrate with high throughput, and that fabricates a semiconductor substrate with reduced adhered contaminants. A planarization apparatus that houses various mechanism elements in semiconductor substrate loading/unloading stage chamber, a rear-surface polishing stage chamber, and a rear-surface grinding stage chamber. The throughput time of the rear-surface polishing stage that simultaneously polishes two substrates is typically about double the throughput time of the rear-surface grinding stage that grinds one substrate.

摘要翻译： 一种平面化装置和方法，其通过以高生产量研磨和抛光衬底的后表面来使衬底平坦化，并且制造具有减少的附着污染物的半导体衬底。 一种在半导体衬底装载/放电室中容纳各种机构元件的平面化装置，后表面抛光台室和后表面研磨台室。 同时抛光两个基材的后表面抛光阶段的生产时间通常是研磨一个基板的后表面研磨阶段的生产时间的两倍。