公开(公告)号：US06349318B1

公开(公告)日：2002-02-19

申请号：US09418217

申请日：1999-10-14

申请人： Scott A. Vanstone ,  Robert J. Lambert ,  Robert Gallant ,  Aleksandar Jurisic ,  Ashok V. Vadekar

发明人： Scott A. Vanstone ,  Robert J. Lambert ,  Robert Gallant ,  Aleksandar Jurisic ,  Ashok V. Vadekar

IPC分类号： G06F700

CPC分类号： G06F9/30014 ,  G06F7/72 ,  G06F7/722 ,  G06F7/724 ,  G06F7/725 ,  G06F9/30036 ,  G06F2207/382

摘要： The present disclosure provides an arithmetic processor having an arithmetic logic unit having a plurality of arithmetic circuits each for performing a group of associated arithmetic operations, such as finite field operations, or modular integer operations. The arithmetic logic unit has an operand input data bus, for receiving operand data thereon and a result data output bus for returning the results of the arithmetic operations thereon. A register file is coupled to the operand data bus and the result data bus. The register file is shared by the plurality of arithmetic circuits. Further a controller is coupled to the ALU and the register file, the controller selecting one of the plurality of arithmetic circuits in response to a mode control signal requesting an arithmetic operation and for controlling data access between the register file and the ALU and whereby the register file is shared by the arithmetic circuits.

摘要翻译： 本公开提供了具有算术逻辑单元的算术处理器，该算术逻辑单元具有多个运算电路，每个运算电路用于执行一组相关联的算术运算，例如有限场运算或模数整数运算。 算术逻辑单元具有用于在其上接收操作数数据的操作数输入数据总线和用于返回其上的算术运算结果的结果数据输出总线。 寄存器文件耦合到操作数数据总线和结果数据总线。 寄存器文件由多个运算电路共享。 此外，控制器耦合到ALU和寄存器文件，控制器响应于请求算术运算的模式控制信号和用于控制寄存器文件和ALU之间的数据访问来选择多个算术电路中的一个，由此寄存器 文件由算术电路共享。