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公开(公告)号：US07475374B1
公开(公告)日：2009-01-06
申请号：US11314698
申请日：2005-12-20
申请人： Scott C. Johnson , Don Walters , Ravinder Rachala , Jerry Moench
发明人： Scott C. Johnson , Don Walters , Ravinder Rachala , Jerry Moench
CPC分类号： G06F17/505 , G06F2217/62
摘要： Various embodiments of methods and systems for providing virtual leaf driver nodes in a clock tree to drive a clock grid of an integrated circuit are disclosed. An integrated circuit may include a large number of clocked elements such as registers, flip-flops, etc. whose operation is synchronized by one or more clocks. For example, an operation performed by circuitry on one side of the die may need to occur at precisely the same time as another operation performed by circuitry on the other side of the die. In order to assure synchronicity of these events, a clock grid may be provided in the IC that is driven by virtual leaf driver nodes. The clock tree driving the clock grid may include a tier of leaf buffers. The output of a leaf buffer may be split, and the branches of the output connected to separate points on the clock grid.
摘要翻译： 公开了用于在时钟树中提供虚拟叶驱动器节点以驱动集成电路的时钟网格的方法和系统的各种实施例。 集成电路可以包括大量的时钟元件，例如寄存器，触发器等，其操作通过一个或多个时钟同步。 例如，由芯片的一侧上的电路执行的操作可能需要在与芯片另一侧上的电路执行的另一操作完全相同的时间进行。 为了确保这些事件的同步性，可以在IC中提供由虚拟叶驱动器节点驱动的时钟网格。 驱动时钟网格的时钟树可以包括一层叶缓冲器。 叶片缓冲区的输出可能被分割，输出的分支连接到时钟网格上的分离点。
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2.发明授权Controller for clock skew determination and reduction based on a lead count over multiple clock cycles 有权控制器用于在多个时钟周期内基于引脚数的时钟偏差确定和减少公开(公告)号：US07770049B1
公开(公告)日：2010-08-03
申请号：US11385328
申请日：2006-03-21
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： Clock skew may be detected measured and compensated for using phase detectors and variable delay adjusters. Phase detectors may be distributed throughout a clock distribution network and may be configured to analyze two clock signals to determine how often one signal leads the other. The output of the phase detectors may be measured and counted over a large number of clock cycles. The difference between the number of times one signal leads or lags behind the other may be used to determine the amount of delay to apply to the leading clock signal in order to minimize (reduce) skew between the two clock signals. The same techniques for detecting and measuring clock skew may also be used to detect and measure jitter in the clock signals. By configuring variable delay adjusters on clock signals, the amount of jitter in the clock signals can be measured or characterized.
摘要翻译： 可以使用相位检测器和可变延迟调节器测量和补偿时钟偏移。 相位检测器可以分布在整个时钟分配网络中，并且可以被配置为分析两个时钟信号以确定一个信号引导另一个信号的频率。 可以在大量时钟周期上测量和计数相位检测器的输出。 可以使用一个信号引导或滞后于另一个信号的次数之间的差异来确定应用于前导时钟信号的延迟量，以便最小化（减少）两个时钟信号之间的偏差。 用于检测和测量时钟偏移的相同技术也可用于检测和测量时钟信号中的抖动。 通过在时钟信号上配置可变延迟调节器，可以测量或表征时钟信号中的抖动量。
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3.发明授权Incrementally adjustable skew and duty cycle correction for clock signals within a clock distribution network 有权对时钟分配网络内的时钟信号进行增量可调偏移和占空比校正公开(公告)号：US07765425B1
公开(公告)日：2010-07-27
申请号：US11385329
申请日：2006-03-21
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A system and method for using variable delay adjusters located at various points across an integrated circuit to measure clock skew and jitter for clock signals of the integrated circuit. A delay controller of the integrated circuit may measure and compensate for clock skew detected between two clock signals by configuring variable delay adjusters located inline with the respective clock signals. Such a delay controller may also use the variable delay adjusters to correct duty cycle errors in a clock signal and may further utilize the variable delay adjusters to measure and characterize jitter detected on the clock signals.
摘要翻译： 一种用于使用位于集成电路上的各个点的可变延迟调节器来测量集成电路的时钟信号的时钟偏移和抖动的系统和方法。 集成电路的延迟控制器可以通过配置与各个时钟信号在一起的可变延迟调节器来测量和补偿在两个时钟信号之间检测到的时钟偏差。 这样的延迟控制器还可以使用可变延迟调整器来校正时钟信号中的占空比误差，并且还可以利用可变延迟调节器来测量和表征在时钟信号上检测到的抖动。
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公开(公告)号：US07652524B2
公开(公告)日：2010-01-26
申请号：US12018297
申请日：2008-01-23
申请人： Dimitry Patent , Ravinder Rachala , Shawn Searles , Lena Ahlen , Matthew Cooke
发明人： Dimitry Patent , Ravinder Rachala , Shawn Searles , Lena Ahlen , Matthew Cooke
CPC分类号： G05F3/262
摘要： An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node.
摘要翻译： 电子电路。 电子电路包括耦合到第一电源电压节点和第二电源电压节点的第一电路支路。 第一电路支路包括被配置为产生第一参考电流的第一参考电流电路和被配置为产生第二参考电流的第二参考电流电路。 电子电路还包括与第一电路支路并联耦合的第二电路支路。 第二电路支路包括耦合以与第一参考电流电路形成电流镜的第一晶体管，以及耦合以与第二参考电流电路形成电流镜的第二晶体管。 第一和第二晶体管中的每一个的源极端子耦合在一起以形成第三电源电压节点。
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公开(公告)号：US20090184696A1
公开(公告)日：2009-07-23
申请号：US12018297
申请日：2008-01-23
申请人： Dimitry Patent , Ravinder Rachala , Shawn Searles , Lena Ahlen , Matthew Cooke
发明人： Dimitry Patent , Ravinder Rachala , Shawn Searles , Lena Ahlen , Matthew Cooke
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node
摘要翻译： 电子电路。 电子电路包括耦合到第一电源电压节点和第二电源电压节点的第一电路支路。 第一电路支路包括被配置为产生第一参考电流的第一参考电流电路和被配置为产生第二参考电流的第二参考电流电路。 电子电路还包括与第一电路支路并联耦合的第二电路支路。 第二电路支路包括耦合以与第一参考电流电路形成电流镜的第一晶体管，以及耦合以与第二参考电流电路形成电流镜的第二晶体管。 第一和第二晶体管中的每一个的源极端子耦合在一起以形成第三电源电压节点
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