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公开(公告)号：US08324742B2
公开(公告)日：2012-12-04
申请号：US12185003
申请日：2008-08-01
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.
摘要翻译： 公开了在不透明层下使用的接触金属层中的IC对准标记和用于形成对准标记的工艺。 对准标记包括几微米宽的接触金属场，在接触蚀刻期间形成的PMD柱阵列，接触金属沉积和选择性接触金属去除过程。 柱子被排列成使得接触金属的所有暴露表面是平面的。 一个配置是矩形阵列，其中每隔一行被横向偏移列间距的一半。 选择柱的水平尺寸以使接触金属填充因子最大化，同时在处理期间向下面的基底提供足够的粘附。 作为接触金属去除过程的结果，接触金属比围绕对准标记的PMD层低至少15纳米。
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公开(公告)号：US20090243122A1
公开(公告)日：2009-10-01
申请号：US12185003
申请日：2008-08-01
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.
摘要翻译： 公开了在不透明层下使用的接触金属层中的IC对准标记和用于形成对准标记的工艺。 对准标记包括几微米宽的接触金属场，在接触蚀刻期间形成的PMD柱阵列，接触金属沉积和选择性接触金属去除过程。 柱子被排列成使得接触金属的所有暴露表面是平面的。 一个配置是矩形阵列，其中每隔一行被横向偏移列间距的一半。 选择柱的水平尺寸以使接触金属填充因子最大化，同时在处理期间向下面的基底提供足够的粘附。 作为接触金属去除过程的结果，接触金属比围绕对准标记的PMD层低至少15纳米。
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公开(公告)号：US08268696B2
公开(公告)日：2012-09-18
申请号：US12964430
申请日：2010-12-09
IPC分类号： H01L21/762
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.
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公开(公告)号：US20110306176A1
公开(公告)日：2011-12-15
申请号：US12964430
申请日：2010-12-09
IPC分类号： H01L21/762
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.
摘要翻译： 公开了在不透明层下使用的接触金属层中的IC对准标记和用于形成对准标记的工艺。 对准标记包括几微米宽的接触金属场，在接触蚀刻，接触金属沉积和选择性接触金属去除过程期间形成在内部的PMD柱阵列。 柱子被排列成使得接触金属的所有暴露表面是平面的。 一个配置是矩形阵列，其中每隔一行被横向偏移列间距的一半。 选择柱的水平尺寸以使接触金属填充因子最大化，同时在处理期间向下面的基底提供足够的粘附。 作为接触金属去除过程的结果，接触金属比围绕对准标记的PMD层低至少15纳米。
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5.发明授权公开(公告)号：US06225134B1
公开(公告)日：2001-05-01
申请号：US09182934
申请日：1998-10-30
申请人： Stephen A. Meisner
发明人： Stephen A. Meisner
IPC分类号： H01L2100
CPC分类号： G03F7/70625
摘要： A method for controlling linewidth in photolithography and in particular during the fabrication of integrated circuits involves separately introducing a linewidth control feature onto a substrate or wafer. This linewidth control feature is preferably introduced after the desired design features or codes and is introduced using the same photomask or reticle as the desired design features. This photomask preferably includes the linewidth control feature at a point outside the maximum field zone as well as a masked pad portion that is in the maximum field zone. This masked pad portion is introduced with the desired design features and serves as a location for subsequent exposure of the linewidth control features. The method allows for the variation in linewidth introduced by the lens to be minimized, or even eliminated, since the same portion of the lens field can be used to expose each linewidth control feature.
摘要翻译： 用于控制光刻中的线宽的方法，特别是在集成电路的制造过程中，分别将衬线控制特征引入到衬底或晶片上。 该线宽控制特征优选地在所需的设计特征或代码之后引入，并且使用与期望的设计特征相同的光掩模或掩模版来引入。 该光掩模优选地包括在最大场区外的点处的线宽控制特征以及处于最大场区中的掩模焊盘部分。 该掩模焊盘部分被引入所需的设计特征并且用作后续曝光线宽控制特征的位置。 该方法允许透镜引入的线宽的变化被最小化或甚至消除，因为可以使用透镜场的相同部分来暴露每个线宽控制特征。
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