公开(公告)号：US10395691B1

公开(公告)日：2019-08-27

申请号：US15680509

申请日：2017-08-18

Applicant: Seagate Technology LLC

Inventor： Kyaw Sin Maung ,  Aaron M. Schmidt

IPC: G06F13/40 ,  G06F15/78 ,  G11B20/18 ,  G11C29/00

Abstract: A data storage drive has two controllers with respective digital control outputs and serial channels. The drive has a serial test channel operable to communicate with a testing system. A switching circuit is coupled to the digital control outputs, the serial channels, and the serial test channel. The switching circuit is configured to, in response to respective combinations of binary values set via the digital control outputs, switch lines of the serial test channel between the respective serial channels of the controllers. The controllers are configured to set the combinations of binary values in response to one or more command received via a receive line of the serial test channel.

公开(公告)号：US10664172B1

公开(公告)日：2020-05-26

申请号：US15844774

申请日：2017-12-18

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Bruce Douglas Buch ,  Kyaw Sin Maung ,  Aaron P. Weyer

IPC: G11B5/54 ,  G06F3/06 ,  G06F12/06 ,  G06F21/60

Abstract: A data storage device includes a first system-on-a-chip (SOC) associated with a first read transducer that accesses one or more magnetic disks of the data storage drive. The first SOC has a first read channel operable to receive data from the first read transducer. A second SOC is associated with a second read transducer that accesses the one or more magnetic disks of the data storage drive independently of the first read transducer. The second SOC has a second read channel operable to receive second data from the second read transducer. The first and second SOCs are coupled via a data bus that facilitates communicating the first and second data to a host via a first host interface.

公开(公告)号：US10020012B1

公开(公告)日：2018-07-10

申请号：US15798541

申请日：2017-10-31

Applicant: Seagate Technology LLC

Inventor： Aaron P. Weyer ,  Bruce Douglas Buch ,  Kyaw Sin Maung ,  Jon D. Trantham ,  Nicholas Paul Mati

IPC: G11B5/09 ,  G11B5/55 ,  G11B5/596 ,  G06F13/42

CPC classification number: G11B5/5526 ,  G06F13/42 ,  G11B5/59616

Abstract: First and second servo control processors are coupled to respective first and second actuators that independently position first and second heads over one or more disks of a data storage drive. The first and second servo control processors are further coupled to first and second low-latency ports. First and second unidirectional buses couple the first and second low-latency ports. The first and second unidirectional busses are operable to isochronously exchange servo positioning data between the first and second servo control processors. The first and second servo control processors each use the servo positioning data to compensate for movement caused by another of the first and second servo control processors.