公开(公告)号：US20170236534A1

公开(公告)日：2017-08-17

申请号：US15043801

申请日：2016-02-15

Applicant: Seagate Technology LLC

Inventor： Xiong Liu ,  Michael R. Montemorra ,  Ralph W. Cross ,  Todd M. Lammers ,  Quan Li ,  Beng Theam Ko ,  Kirill Rivkin ,  Mourad Benakli

IPC: G11B5/09 ,  G11B20/12 ,  G11B5/012

CPC classification number: G11B5/09 ,  G11B5/012 ,  G11B20/10027 ,  G11B20/1217 ,  G11B20/1426

Abstract: Method and apparatus for enhancing write current switching efficiencies during data write operations in a data storage device. In some embodiments, write data are described in the form a sequence of symbols of nT length where T is a channel clock rate and n is an integer over a selected range. Bi-directional write currents are applied to a write element to record the sequence of symbols to a storage medium. The write currents are switched between a first rail current and a second rail current for alternating symbols. The write currents are further transitioned to an intermediate current value for at least one channel clock period immediately preceding a next occurrence of a symbol boundary between an adjacent pair of symbols in the sequence.

公开(公告)号：US09905251B2

公开(公告)日：2018-02-27

申请号：US15043801

申请日：2016-02-15

Applicant: Seagate Technology LLC

Inventor： Xiong Liu ,  Michael R. Montemorra ,  Ralph W. Cross ,  Todd M. Lammers ,  Quan Li ,  Beng Theam Ko ,  Kirill Rivkin ,  Mourad Benakli

IPC: G11B5/09 ,  G11B5/012 ,  G11B20/12

CPC classification number: G11B5/09 ,  G11B5/012 ,  G11B20/10027 ,  G11B20/1217 ,  G11B20/1426

Abstract: Method and apparatus for enhancing write current switching efficiencies during data write operations in a data storage device. In some embodiments, write data are described in the form a sequence of symbols of nT length where T is a channel clock rate and n is an integer over a selected range. Bi-directional write currents are applied to a write element to record the sequence of symbols to a storage medium. The write currents are switched between a first rail current and a second rail current for alternating symbols. The write currents are further transitioned to an intermediate current value for at least one channel clock period immediately preceding a next occurrence of a symbol boundary between an adjacent pair of symbols in the sequence.