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公开(公告)号：US10559321B1
公开(公告)日：2020-02-11
申请号：US16274669
申请日：2019-02-13
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado , Marcus Marrow , Vincent B Ashe
Abstract: In one implementation, the disclosure provides a system including a first circuit to compute a timing error based on a received error signal and an estimated interference signal and a timing loop filter to output a frequency offset and a phase shift based on the timing error received as input. The system also includes a phase accumulator to accumulate at least a phase shift to generate a sample index and phase and an interpolation filter to generate samples of a side track signal using the sample index and phase.
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