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    Determination of data rate and data type in a high-level electronic design
    1.
    发明授权
    Determination of data rate and data type in a high-level electronic design 有权
    在高级电子设计中确定数据速率和数据类型

    公开(公告)号：US07685554B1

    公开(公告)日：2010-03-23

    申请号：US11185125

    申请日：2005-07-20

    申请人： Sean A. Kelly ,  Roger B. Milne ,  Jeffrey D. Stroomer ,  Sreekanth Juttu

    发明人： Sean A. Kelly ,  Roger B. Milne ,  Jeffrey D. Stroomer ,  Sreekanth Juttu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Determining data rates and data types in a an electronic design. In one embodiment, an electronic design is created in a memory arrangement in response to user input. The electronic design includes a plurality of functional blocks and a plurality of nets connecting the functional blocks. In response to user input, an output data rate and an output data type of data output from at least one of the functional blocks are determined. The input data rate and input data type to each functional block coupled via a net to the at least one functional block are equal to the output data rate and output data type, respectively, from the at least one functional block. For each functional block, an output data rate and output data type are determined as a function of the input data rate and the input data type of the functional block.

    摘要翻译： 确定电子设计中的数据速率和数据类型。 在一个实施例中，响应于用户输入在存储器装置中创建电子设计。 电子设计包括多个功能块和连接功能块的多个网。 响应于用户输入，确定从至少一个功能块输出的输出数据速率和输出数据类型的数据。 经由网络耦合到至少一个功能块的每个功能块的输入数据速率和输入数据类型分别等于来自至少一个功能块的输出数据速率和输出数据类型。 对于每个功能块，输出数据速率和输出数据类型根据输入数据速率和功能块的输入数据类型来确定。

    Using scripts for netlisting in a high-level modeling system
    2.
    发明授权
    Using scripts for netlisting in a high-level modeling system 有权
    在高级建模系统中使用脚本进行网页列表

    公开(公告)号：US07797677B1

    公开(公告)日：2010-09-14

    申请号：US11268801

    申请日：2005-11-08

    申请人： Jonathan B. Ballagh ,  Sean A. Kelly ,  Roger B. Milne ,  Shay Ping Seng ,  Jeffrey D. Stroomer

    发明人： Jonathan B. Ballagh ,  Sean A. Kelly ,  Roger B. Milne ,  Shay Ping Seng ,  Jeffrey D. Stroomer

    IPC分类号： G06F9/44

    CPC分类号： G06F9/543 ,  G06F9/541 ,  G06F17/5054

    摘要： A method of passing data among modules of a heterogeneous software system can include identifying a scripted function to be executed within the heterogeneous software system and building a wrapper script by embedding a call to the scripted function and an XTable object associated with the scripted function within the wrapper script. The method further can include executing the wrapper script thereby causing the scripted function to execute and receiving a result from execution of the scripted function.

    摘要翻译： 在异构软件系统的模块之间传递数据的方法可以包括识别要在异构软件系统内执行的脚本化功能，以及通过嵌入对脚本化功能的调用和与脚本化功能相关联的XTable对象来构建包装器脚本 包装脚本 该方法还可以包括执行包装器脚本，从而使脚本化功能执行并从脚本化功能的执行接收结果。

    Translation of high-level circuit design blocks into hardware description language
    3.
    发明授权
    Translation of high-level circuit design blocks into hardware description language 有权
    将高级电路设计块翻译成硬件描述语言

    公开(公告)号：US07386814B1

    公开(公告)日：2008-06-10

    申请号：US11054864

    申请日：2005-02-10

    申请人： Jeffrey D. Stroomer ,  Roger B. Milne ,  Isaac W. Foraker ,  Sean A. Kelly

    发明人： Jeffrey D. Stroomer ,  Roger B. Milne ,  Isaac W. Foraker ,  Sean A. Kelly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.

    摘要翻译： 将高级设计块翻译成硬件描述语言（HDL）的设计规范。 高级设计中的每个块都分配给一个组。 一组属性在组中的块之间是相同的。 对于每组块，确定组中至少两个块的子块上具有不同值的相应参数集合。 为每个组生成HDL规范。 组的HDL规范对参数集中的每个参数都有参数输入。

    Translation of high-level circuit design blocks into hardware description language
    4.
    发明授权
    Translation of high-level circuit design blocks into hardware description language 失效
    将高级电路设计块翻译成硬件描述语言

    公开(公告)号：US07685541B1

    公开(公告)日：2010-03-23

    申请号：US12113231

    申请日：2008-05-01

    申请人： Jeffrey D. Stroomer ,  Roger B. Milne ,  Isaac W. Foraker ,  Sean A. Kelly

    发明人： Jeffrey D. Stroomer ,  Roger B. Milne ,  Isaac W. Foraker ,  Sean A. Kelly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.

    摘要翻译： 将高级设计块翻译成硬件描述语言（HDL）的设计规范。 高级设计中的每个块都分配给一个组。 一组属性在组中的块之间是相同的。 对于每组块，确定组中至少两个块的子块上具有不同值的相应参数集合。 为每个组生成HDL规范。 组的HDL规范对参数集中的每个参数都有参数输入。

    Transformation of graphs representing an electronic design in a high modeling system
    6.
    发明授权
    Transformation of graphs representing an electronic design in a high modeling system 有权
    在高建模系统中转换代表电子设计的图形

    公开(公告)号：US07444603B1

    公开(公告)日：2008-10-28

    申请号：US11639547

    申请日：2006-12-15

    申请人： Sean A. Kelly ,  Roger B. Milne ,  Jeffrey D. Stroomer ,  Jonathan B. Ballagh

    发明人： Sean A. Kelly ,  Roger B. Milne ,  Jeffrey D. Stroomer ,  Jonathan B. Ballagh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/509

    摘要： Methods and apparatus are provided for processing an electronic design in a high level modeling system. A first graph is generated, with the nodes representing basic elements of the electronic design and including a shared node representing the basic element of a block, a port, or a network of the electronic design. Multiple second graphs are generated modeling different aspects of the electronic design. A first and second member of the nodes and edges of respective ones of the second graphs are each associated with the shared node of the first graph. The different aspects of the electronic design of the second-type graphs transformed, with a first attribute of one of the second graphs written to the shared node using the first member, and a second attribute of another of the second graphs determined as a function of the first attribute read from the shared node using the second member.

    摘要翻译： 提供了用于在高级建模系统中处理电子设计的方法和装置。 生成第一图，其中节点表示电子设计的基本元素，并且包括表示电子设计的块，端口或网络的基本元素的共享节点。 生成多个第二个图形来建立电子设计的不同方面。 各个第二图的各节点和边的第一和第二成员各自与第一图的共享节点相关联。 第二类图的电子设计的不同方面被转换，其中使用第一成员写入共享节点的第二图形之一的第一属性和另一第二图形的第二属性被确定为 使用第二个成员从共享节点读取的第一个属性。

    Specification of the hierarchy, connectivity, and graphical representation of a circuit design
    8.
    发明授权
    Specification of the hierarchy, connectivity, and graphical representation of a circuit design 有权
    电路设计的层次结构，连接性和图形表示的规范

    公开(公告)号：US07003751B1

    公开(公告)日：2006-02-21

    申请号：US10340498

    申请日：2003-01-10

    申请人： Jeffrey D. Stroomer ,  Roger B. Milne ,  Jonathan B. Ballagh ,  Haibing Ma ,  L. James Hwang ,  Nabeel Shirazi

    发明人： Jeffrey D. Stroomer ,  Roger B. Milne ,  Jonathan B. Ballagh ,  Haibing Ma ,  L. James Hwang ,  Nabeel Shirazi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.

    摘要翻译： 用于创建电路设计的方法和装置。 面向对象的程序实例化建模电路设计的多个对象。 对象具有描述多个模块的层次属性，连接属性和显示属性。 层次结构属性定义模块之间的父子关系，连接属性定义模块之间的输入输出连接，显示属性定义模块的布局以供查看。 每个对象具有用于以所选格式生成设计规范的关联方法。 当执行程序时，设计规范是从对象集合生成的。 根据可用工具的功能，根据面向对象程序或设计规范的显示属性显示模块和逻辑元素。

    Translation of an electronic integrated circuit design into hardware
    9.
    发明授权
    Translation of an electronic integrated circuit design into hardware 有权
    将电子集成电路设计翻译成硬件

    公开(公告)号：US07207015B1

    公开(公告)日：2007-04-17

    申请号：US10618037

    申请日：2003-07-11

    申请人： Jonathan B. Ballagh ,  Roger B. Milne ,  Jeffrey D. Stroomer

    发明人： Jonathan B. Ballagh ,  Roger B. Milne ,  Jeffrey D. Stroomer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： Translation of an electronic design of an integrated circuit into circuit description language is described. In an example, a connection among circuit descriptions representing behavior of circuit elements in the electronic design is identified. The connection is associated with an identifier. The electronic design is then translated into a circuit description language representation, where the connection is implemented within the circuit description language representation using the identifier. In another example, an implicit circuit description representing behavior of circuit elements within the electronic design are identified. Explicit circuit descriptions within the electronic design are augmented with an addition circuit description. The electronic design is then translated into a circuit description language representation.

    摘要翻译： 将集成电路的电子设计翻译成电路描述语言。 在一个示例中，识别表示电子设计中电路元件的行为的电路描述之间的连接。 连接与标识符相关联。 然后将电子设计转换成电路描述语言表示，其中使用标识符在电路描述语言表示内实现连接。 在另一示例中，识别表示电子设计内的电路元件的行为的隐式电路描述。 电子设计中的显式电路描述增加了加法电路描述。 然后将电子设计转换为电路描述语言表示。

    Translation of an electronic integrated circuit design into hardware description language using circuit description template
    10.
    发明授权
    Translation of an electronic integrated circuit design into hardware description language using circuit description template 有权
    将电子集成电路设计翻译成使用电路描述模板的硬件描述语言

    公开(公告)号：US07007261B1

    公开(公告)日：2006-02-28

    申请号：US10388711

    申请日：2003-03-14

    申请人： Jonathan B. Ballagh ,  Roger B. Milne ,  Jeffrey D. Stroomer

    发明人： Jonathan B. Ballagh ,  Roger B. Milne ,  Jeffrey D. Stroomer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Method, apparatus, and computer readable medium for translating an electronic design of an integrated circuit into circuit description language is described. The electronic design includes a plurality of circuit descriptions representing behavior of circuit elements. A circuit description template is associated with a circuit description of the plurality of circuit descriptions. The circuit description template includes a first portion for fixed attributes of the circuit description and a second portion for variable attributes of the circuit description. One or more text processors are associated with the circuit description template. Variable attributes of the circuit description are related to the second portion of the circuit description template to produce a data structure. The circuit description template is processed using the one or more text processors with the data structure as parametric input.

    摘要翻译： 描述了用于将集成电路的电子设计转换为电路描述语言的方法，装置和计算机可读介质。 电子设计包括表示电路元件的行为的多个电路描述。 电路描述模板与多个电路描述的电路描述相关联。 电路描述模板包括用于电路描述的固定属性的第一部分和用于电路描述的可变属性的第二部分。 一个或多个文本处理器与电路描述模板相关联。 电路描述的可变属性与电路描述模板的第二部分相关，以产生数据结构。 使用具有数据结构作为参数输入的一个或多个文本处理器来处理电路描述模板。