公开(公告)号：US20210408355A1

公开(公告)日：2021-12-30

申请号：US17472821

申请日：2021-09-13

申请人： SeeQC, Inc.

发明人： Daniel Yohannes ,  Denis Amparo ,  Oleksandr Chernyashevskyy ,  Oleg Mukhanov ,  Mario Renzullo ,  Andrei Talalaeskii ,  Igor Vernik ,  John Vivalda ,  Jason Walter

IPC分类号： H01L39/04 ,  H01L23/00 ,  H01L39/22 ,  H01L39/24

摘要： A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

公开(公告)号：US20220393089A1

公开(公告)日：2022-12-08

申请号：US17337394

申请日：2021-06-02

申请人： SeeQC, Inc.

发明人： Daniel Yohannes ,  Mario Renzullo ,  John Vivalda ,  Alexander Kirichenko

IPC分类号： H01L39/22 ,  H01L39/24 ,  H01L39/02 ,  G06N10/00

摘要： Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

公开(公告)号：US11508896B1

公开(公告)日：2022-11-22

申请号：US17337394

申请日：2021-06-02

申请人： SeeQC, Inc.

发明人： Daniel Yohannes ,  Mario Renzullo ,  John Vivalda ,  Alexander Kirichenko

IPC分类号： H01L39/22 ,  H01L39/24 ,  G06N10/00 ,  H01L39/02

摘要： Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

公开(公告)号：US11121302B2

公开(公告)日：2021-09-14

申请号：US16599985

申请日：2019-10-11

申请人： SeeQC, Inc.

发明人： Daniel Yohannes ,  Denis Amparo ,  Oleksandr Chernyashevskyy ,  Oleg Mukhanov ,  Mario Renzullo ,  Andrei Talalaeskii ,  Igor Vernik ,  John Vivalda ,  Jason Walter

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L31/0256 ,  H01L39/22 ,  H01L39/04 ,  H01L23/00 ,  H01L39/24

摘要： A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.