公开(公告)号：US07120412B2

公开(公告)日：2006-10-10

申请号：US10303384

申请日：2002-11-25

Applicant: Seema Butala Anand

Inventor： Seema Butala Anand

IPC: H04B1/06 ,  H04B1/16

CPC classification number: H03L7/099 ,  H03B2201/025 ,  H03J2200/10 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/187 ,  H04B1/30 ,  H04B1/408

Abstract: A phase-locked loop circuit includes an array of selectable capacitors formed within the phase-locked loop circuit to enable the phase-locked loop circuit to provide a degree of coarse frequency control by adding or removing capacitors and a degree of fine frequency control by sinking or sourcing current from a charge pump into a loop filter. A finite state machine is provided within a voltage controlled oscillator calibration circuit that communicates with an external baseband processor to initiate a calibration process, and further to determine how many capacitors of an array of capacitors if formed within the phase-locked loop circuit should be coupled to provide the coarse frequency control.