公开(公告)号：US11757491B2

公开(公告)日：2023-09-12

申请号：US17647285

申请日：2022-01-06

Applicant: NXP B.V.

Inventor： Markus Wobak ,  Johannes Stahl ,  Ulrich Andreas Muehlmann

IPC: H04B5/00 ,  H04B1/408 ,  H04B1/525

CPC classification number: H04B5/0031 ,  H04B1/408 ,  H04B1/525 ,  H04B5/0043 ,  H04B5/0062

Abstract: In accordance with a first aspect, a communication device is provided, comprising: a transmitter configured to transmit one or more radio frequency signal pulses to an external communication device; a receiver configured to receive one or more response signals in response to the radio frequency signal pulses transmitted by the transmitter; a signal analyzer configured to detect one or more characteristics of the response signals, to compare the detected characteristics with predefined reference characteristics and to generate an output indicative of a result of comparing the detected characteristics with the predefined reference characteristics; a processing unit configured to determine at least one category to which the external communication device belongs based on the output generated by the signal analyzer. In accordance with a second aspect, a corresponding method of operating a communication device is conceived. In accordance with a third aspect, a corresponding computer program is provided.

公开(公告)号：US20180205412A1

公开(公告)日：2018-07-19

申请号：US15253196

申请日：2016-08-31

Applicant: Ming Yu Lin ,  Qiang Li

Inventor： Ming Yu Lin ,  Qiang Li

IPC: H04B1/403 ,  H04B1/3805 ,  H04B1/408

CPC classification number: H04B1/406 ,  H04B1/3805 ,  H04B1/408 ,  H04W88/06

Abstract: A wireless transceiver system is disclosed. The system includes a narrow band transmitter. The narrow band transmitter includes at least a delta sigma phased locked loop (delta-sigma PLL) circuit and a non-linear low-power amplifier, where an output of the delta-sigma PLL is coupled to an input of the non-linear low-power amplifier. The system further includes a wide band transmitter. The wide band transmitter includes at least a digital to analog converter (DAC), a low pass filter, a local oscillator mixer and a linear high power amplifier, where an output of the DAC is coupled to an input of the low pass filter and an output of the low pass filter is coupled to an input of the local oscillator mixer and wherein an output of the local oscillator mixer is coupled to an input of the linear high power amplifier.

公开(公告)号：US09692428B2

公开(公告)日：2017-06-27

申请号：US14137366

申请日：2013-12-20

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

Inventor： Sudipto Chakraborty ,  Jens Graul

IPC: H03L7/08 ,  H03L7/18 ,  H03L7/099 ,  H03L7/089 ,  H03L7/23 ,  H03L7/10 ,  H04B1/403 ,  H04B1/408 ,  H04B1/50

CPC classification number: H03L7/0802 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/104 ,  H03L7/18 ,  H03L7/235 ,  H04B1/403 ,  H04B1/408 ,  H04B1/50

Abstract: A self-calibrating shared-component dual synthesizer includes, for example, two frequency synthesizers that are adapted to operate (respectively) in transmit (TX) and receive (RX) modes. Each synthesizer can be selectively arranged to vary and optimize the phase noise in accordance with the TX and RX requirements associated with each mode as well as independently optimized for flexible low area floorplan to achieve low power, spectral fidelity and reduced test time, low cost built in self-calibration. The two frequency synthesizers are also adapted to provide a built-in self-test signals used for intermodulation testing and calibration.

公开(公告)号：US09419673B2

公开(公告)日：2016-08-16

申请号：US14386749

申请日：2013-03-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Cedric Dehos ,  Laurent Dussopt ,  Alexandre Siligaris ,  Pierre Vincent

IPC: H04B1/40 ,  H04B1/408 ,  H01L23/66 ,  H01L25/16 ,  H01Q23/00 ,  H04B1/04

CPC classification number: H04B1/408 ,  H01L23/66 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01Q23/00 ,  H04B1/0483

Abstract: In the field of millimeter band transmitting/receiving systems for a high-speed contactless transmission, an architecture is provided with a common processing circuit supplying modulation signals and a plurality of transmitting/receiving integrated circuits, all identical to one another, receiving these signals, and also a common clock. The transmitting/receiving integrated circuits each comprise: an oscillator locked with the clock signal to produce a carrier frequency, a transmit channel comprising a first controllable phase shift circuit, a frequency transposition to the carrier frequency, and a power amplifier, a receive channel comprising a low noise amplifier, a frequency transposition from the carrier frequency, and a second controllable phase shift circuit. An antenna is associated with each transmitting/receiving circuit.

Abstract translation: 在用于高速非接触式传输的毫米波段发射/接收系统领域中，架构设置有提供调制信号的公共处理电路和多个彼此相同的发送/接收集成电路，接收这些信号， 也是一个普通的时钟。 发送/接收集成电路各自包括：与时钟信号锁定以产生载波频率的振荡器，包括第一可控相移电路，到载波频率的频率转置的发射信道和功率放大器，包括 低噪声放大器，来自载波频率的频率转置和第二可控相移电路。 天线与每个发射/接收电路相关联。

公开(公告)号：US09130737B1

公开(公告)日：2015-09-08

申请号：US14610271

申请日：2015-01-30

Applicant: Panasonic Corporation

Inventor： Koji Takinami ,  Takayuki Tsukizawa ,  Kenji Miyanaga ,  Shunsuke Hirano

IPC: H03D3/24 ,  H04L7/033 ,  H04B1/405 ,  H04B1/00 ,  H03L7/18 ,  H03L7/193 ,  H03L7/16

CPC classification number: H03L7/16 ,  H03L7/18 ,  H03L7/193 ,  H04B1/403 ,  H04B1/408

Abstract: A signal-generating circuit includes a voltage-controlled oscillator that generates an oscillated signal; a first frequency divider that generates a first divided signal by dividing the oscillated signal; a second frequency divider that generates a second divided signal by dividing the divided signal; a phase comparator that receives as input the second divided signal and a reference signal and outputs two signals corresponding to a phase difference therebetween; a loop filter that extracts a low frequency signal between the two signals to be output to the voltage-controlled oscillator; a third frequency divider that generates a third divided signal by dividing the first divided signal; a first frequency converter that generates a first frequency converted signal by multiplying the oscillated signal by the third divided signal; and a first multiplier that generates a multiplied signal by multiplying the first frequency converted signal by a first multiplication number.

Abstract translation: 信号发生电路包括产生振荡信号的压控振荡器; 第一分频器，通过分频振荡信号产生第一分频信号; 第二分频器，通过划分分频信号产生第二分频信号; 相位比较器，接收第二分频信号和参考信号作为输入，并输出对应于它们之间的相位差的两个信号; 环路滤波器，提取要输出到压控振荡器的两个信号之间的低频信号; 第三分频器，通过划分第一分频信号产生第三分频信号; 第一频率转换器，其通过将所述振荡信号乘以所述第三分频信号来产生第一频率转换信号; 以及第一乘法器，通过将第一频率转换信号乘以第一乘法数来产生相乘的信号。

公开(公告)号：US20150180594A1

公开(公告)日：2015-06-25

申请号：US14137366

申请日：2013-12-20

Applicant: Texas Instruments Deutschland GmbH ,  Texas Instruments Incorporated

Inventor： Sudipto Chakraborty ,  Jens Graul

IPC: H04B17/14 ,  H04B17/24 ,  H04B17/21 ,  H03L7/099 ,  H03L7/08

CPC classification number: H03L7/0802 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/104 ,  H03L7/18 ,  H03L7/235 ,  H04B1/403 ,  H04B1/408 ,  H04B1/50

Abstract: A self-calibrating shared-component dual synthesizer includes, for example, two frequency synthesizers that are adapted to operate (respectively) in transmit (TX) and receive (RX) modes. Each synthesizer can be selectively arranged to vary and optimize the phase noise in accordance with the TX and RX requirements associated with each mode as well as independently optimized for flexible low area floorplan to achieve low power, spectral fidelity and reduced test time, low cost built in self-calibration. The two frequency synthesizers are also adapted to provide a built-in self-test signals used for intermodulation testing and calibration.

Abstract translation: 自校准共享部件双合成器包括例如适于在发射（TX）和接收（RX）模式中分别操作的两个频率合成器。 每个合成器可以选择性地布置成根据与每个模式相关联的TX和RX要求来改变和优化相位噪声，并且针对灵活的低面积平面图进行独立优化，以实现低功率，频谱保真度和缩短的测试时间，低成本内置 进行自校准。 两个频率合成器也适用于提供用于互调测试和校准的内置自测信号。

公开(公告)号：US07848395B2

公开(公告)日：2010-12-07

申请号：US11465760

申请日：2006-08-18

Applicant: Dean Lawrence Cook ,  Kenneth V. Buer

Inventor： Dean Lawrence Cook ,  Kenneth V. Buer

IPC: H04L5/16 ,  H04B1/38

CPC classification number: H04B1/408 ,  H04B1/403

Abstract: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signals. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. In one exemplary embodiment, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In another exemplary embodiment, multiple signals may be transmitted over multiple cables. Additionally, multiple signals over one or more cables may be transmitted at or below 3 GHz.

Abstract translation: 提供频率计划用于收发器中的特定用途。 有利地，可以使用单个振荡器来产生期望的频率信号。 一个或多个功率分配器接收信号并且将信号等分成具有基本上等于原始频率的频率的第一和第二信号。 收发器的每个臂上的乘数接收信号并增加信号的频率。 在一个示例性实施例中，具有不同频率的多个信号可以通过相同的电缆传输，部分是由于信号之间产生的频率间隔。 在另一示例性实施例中，多个信号可以通过多个电缆传输。 此外，一根或多根电缆上的多个信号可以在3 GHz或以下传输。

公开(公告)号：US07693230B2

公开(公告)日：2010-04-06

申请号：US11358395

申请日：2006-02-22

Applicant: David F. Sorrells ,  Michael J. Bultman ,  Robert W. Cook ,  Richard C. Looke ,  Charley D. Moses, Jr. ,  Gregory S. Rawlins ,  Michael W. Rawlins

Inventor： David F. Sorrells ,  Michael J. Bultman ,  Robert W. Cook ,  Richard C. Looke ,  Charley D. Moses, Jr. ,  Gregory S. Rawlins ,  Michael W. Rawlins

IPC: H04L27/04 ,  H04L27/12 ,  H04L27/20

CPC classification number: H04B1/04 ,  H03C3/40 ,  H03D3/006 ,  H03D7/00 ,  H04B1/408 ,  H04B2001/0491 ,  H04L25/03

Abstract: A balanced transmitter up-converts I and Q baseband signals directly from baseband-to-RF. The up-conversion process is sufficiently linear that no IF processing is required, even in communications applications that have stringent requirements on spectral growth. In operation, the balanced modulator sub-harmonically samples the I and Q baseband signals in a balanced and differential manner, resulting in harmonically rich signal. The harmonically rich signal contains multiple harmonic images that repeat at multiples of the sampling frequency, where each harmonic contains the necessary information to reconstruct the I and Q baseband signals. The differential sampling is performed according to a first and second control signals that are phase shifted with respect to each other. In embodiments of the invention, the control signals have pulse widths (or apertures) that operate to improve energy transfer to a desired harmonic in the harmonically rich signal. A bandpass filter can then be utilized to select the desired harmonic of interest from the harmonically rich signal.

公开(公告)号：US07583179B2

公开(公告)日：2009-09-01

申请号：US11154231

申请日：2005-06-16

Applicant: Jiangfeng Wu ,  Donald Edward Major

Inventor： Jiangfeng Wu ,  Donald Edward Major

IPC: H04Q5/22

CPC classification number: G06K7/0008 ,  H04B1/30 ,  H04B1/408

Abstract: A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.

Abstract translation: 用于RFID读取器的收发器和用于RFID应答器（标签）的收发器允许两个设备之间的通信。 RFID阅读器使用模拟前端和数字后端。 在收发器的接收器部分中，RFID读取器的前端使用一对下变频混频器将接收的信号解调为同相（I）和正交（Q）分量和模数转换器（ADC） ）数字化信号。 后端的数字信号处理器（DSP）处理数字信号，并使用匹配滤波器进行数据检测。 RFID标签从读取器接收电感耦合信号，并且标签的接收器部分使用采用模拟比较器和采样和保持电路来检测接收信号的脉冲/电平检测器。 数字解码器/控制器用于对输入数据进行解码并建立脉冲/电平检测器的采样时钟。 自动增益控制（AGC）电路根据接收到的信号强度调整接收机增益，并控制磁耦合电路的调谐。

公开(公告)号：US07519333B2

公开(公告)日：2009-04-14

申请号：US09785759

申请日：2001-02-16

Applicant: Ranjit Gharpurey

Inventor： Ranjit Gharpurey

IPC: H04B1/44 ,  H04B1/40

CPC classification number: H04B1/408

Abstract: A radio such as a frequency division duplex (FDD) radio (100) has a first local oscillator (LO1I and LO1Q) that is set to coincide with the transmitter section's (126) center frequency or a sub-harmonic thereof. In this way, after the first down-conversion, the transmit interferer is converted to DC, where it can be effectively removed using a simple high-pass filter (110, 112) such as a DC blocking capacitor. Image rejection is achieved by the use of a two-step down-conversion approach that uses quadrature local oscillators to implement a single-sideband down-converter.