公开(公告)号：US20150168970A1

公开(公告)日：2015-06-18

申请号：US14569114

申请日：2014-12-12

申请人： Seiko Instruments Inc.

发明人： Tsutomu TOMIOKA ,  Masakazu SUGIURA ,  Daisuke YOSHIOKA ,  Hiroki CHUMAN

IPC分类号： G05F1/56

CPC分类号： G05F1/56 ,  G05F1/567

摘要： Provided is a voltage regulator capable of preventing an output voltage from being increased even when a leakage current flows in an output transistor. The voltage regulator includes a leakage current control circuit. The leakage current control circuit includes an NMOS transistor connected to an output terminal of the voltage regulator. When the output voltage of the voltage regulator increases due to the leakage current of the output transistor, the leakage current control circuit causes the leakage current to flow through the NMOS transistor, to thereby prevent an increase in output voltage.

摘要翻译： 提供了即使当漏电流在输出晶体管中流动时也能够防止输出电压增加的电压调节器。 电压调节器包括漏电流控制电路。 泄漏电流控制电路包括连接到电压调节器的输出端的NMOS晶体管。 当电压调节器的输出电压由于输出晶体管的漏电流而增加时，漏电流控制电路使漏电流流过NMOS晶体管，从而防止输出电压的增加。