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公开(公告)号：US09369117B2
公开(公告)日：2016-06-14
申请号：US14976626
申请日：2015-12-21
Applicant: Seiko Instruments Inc.
Inventor： Yotaro Nihei , Tomoyuki Yokoyama
Abstract: Provided is a voltage regulator which consumes low power and uses an NMOS transistor as an output transistor. A delay circuit includes, between a constant current circuit and a capacitor, a depletion type NMOS transistor having a gate and a back gate each connected to a ground terminal, the constant current circuit including a depletion type NMOS transistor and a resistor connected between each of a gate and a back gate of the depletion type NMOS transistor and a source thereof.
Abstract translation: 提供了消耗低功率并使用NMOS晶体管作为输出晶体管的电压调节器。 延迟电路在恒流电路和电容器之间包括具有各自连接到接地端子的栅极和背栅的耗尽型NMOS晶体管，恒流电路包括耗尽型NMOS晶体管和连接在每个的电阻之间的电阻器 耗尽型NMOS晶体管的栅极和背栅极及其源极。
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公开(公告)号：US10061335B2
公开(公告)日：2018-08-28
申请号：US14287999
申请日：2014-05-27
Applicant: Seiko Instruments Inc.
Inventor： Tadashi Kurozo , Tomoyuki Yokoyama
CPC classification number: G05F1/575
Abstract: Provided is a voltage regulator having satisfactory transient response characteristics. The voltage regulator includes: a first amplifier for detecting that undershoot occurs in an output voltage; a second amplifier for detecting that overshoot occurs in the output voltage; a first constant current circuit for increasing a bias current of an error amplifier circuit by a first amount for a first time period in response to a signal determined based on one of an output signal of the first amplifier and an output signal of the second amplifier; a second constant current circuit for increasing the bias current of the error amplifier circuit by a second amount larger than the first amount for a second time period shorter than the first time period in response to a signal determined based on the output signal of the first amplifier; and a first switch circuit for pulling up a gate of an output transistor in response to a signal determined based on the output signal of the second amplifier.
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