公开(公告)号：US11099591B1

公开(公告)日：2021-08-24

申请号：US16567858

申请日：2019-09-11

申请人： Selçuk Köse ,  Longfei Wang ,  S. Karen Khatamifard ,  Ulya R. Karpuzcu

发明人： Selçuk Köse ,  Longfei Wang ,  S. Karen Khatamifard ,  Ulya R. Karpuzcu

IPC分类号： G05F1/59 ,  G05F1/614 ,  G05F1/563 ,  G05F1/56 ,  G05F1/575 ,  G05F1/565

摘要： A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.