公开(公告)号：US20230320135A1

公开(公告)日：2023-10-05

申请号：US18127198

申请日：2023-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuharu HOSAKA ,  Masami JINTYOU ,  Takahiro IGUCHI ,  Chieko MISAMA ,  Ami SATO ,  Masayoshi DOBASHI

IPC: H10K59/121 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H10K59/1201

Abstract: Provided is a semiconductor device having a high degree of integration, which includes first and second transistors and a first insulating layer. The first transistor includes a first semiconductor layer, a second insulating layer, and first to third conductive layers. The second transistor includes a second semiconductor layer, a third insulating layer, and fourth to sixth conductive layers. The first insulating layer includes a region in contact with the first semiconductor layer and the first conductive layer and includes an opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The second conductive layer is positioned over the first insulating layer. The third conductive layer is positioned over the first semiconductor layer and includes a region overlapping with the inner wall of the opening with the second insulating layer positioned therebetween. The second semiconductor layer is positioned over the first insulating layer and in contact with side and top surfaces of a side end portion of the fourth conductive layer and side and top surfaces of a side end portion of the fifth conductive layer; the side end portions face each other. The sixth conductive layer is positioned over the second semiconductor layer with the third insulating layer positioned therebetween. The first transistor is electrically connected to the second transistor.