公开(公告)号：US20160373089A1

公开(公告)日：2016-12-22

申请号：US15254373

申请日：2016-09-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yukio MAEHASHI ,  Siichi YONEDA ,  Wataru UESUGI

IPC: H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356 ,  H03K3/356104

Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.