公开(公告)号：US06569737B2

公开(公告)日：2003-05-27

申请号：US09818759

申请日：2001-03-28

申请人： Seong-Hyung Park ,  Myoung-Jun Jang

发明人： Seong-Hyung Park ,  Myoung-Jun Jang

IPC分类号： H01L21336

CPC分类号： H01L29/66621 ,  H01L21/76237

摘要： Forming a semiconductor transistor by embedding the gate electrode into the substrate so that a step difference between the gate electrode and the source or drain region is reduced. Device isolation areas are defined by forming at least two first trenches having a first depth. The gate electrode is formed in a second trench located between the first trenches at a second depth being less than the first depth. A source and a drain are respectively formed between the gate electrode and the device isolation areas. The gate electrically connects the source and drain to form a semiconductor channel in the substrate.

摘要翻译： 通过将栅电极嵌入衬底中形成半导体晶体管，使得栅电极和源极或漏极区之间的阶跃差减小。 通过形成具有第一深度的至少两个第一沟槽来限定器件隔离区域。 栅极电极形成在位于第一沟槽之间的第二沟槽中，第二沟槽的第二深度小于第一深度。 源极和漏极分别形成在栅电极和器件隔离区之间。 栅极电连接源极和漏极，以在衬底中形成半导体沟道。