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公开(公告)号：US10565283B2
公开(公告)日：2020-02-18
申请号：US13976766
申请日：2011-12-22
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four consecutive non-negative integers in numerical order. In an aspect, the instruction does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location. Other methods, apparatus, systems, and instructions are disclosed.
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2.发明申请公开(公告)号：US20130275727A1
公开(公告)日：2013-10-17
申请号：US13976580
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 方面的方法包括接收指令。 该指令指示整数步长，表示整数偏移，并指示目的地存储位置。 结果存储在目的地存储位置以响应该指令。 结果包括以数字顺序的至少四个整数的序列，其中至少四个整数中的最小的整数与零与整数偏移不同，并且具有与整数步长不同的连续位置中的序列的所有整数。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US09898283B2
公开(公告)日：2018-02-20
申请号：US13976580
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
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公开(公告)号：US09639354B2
公开(公告)日：2017-05-02
申请号：US13977356
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
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5.发明申请Packed Data Rearrangement Control Indexes Generation Processors, Methods, Systems and Instructions 有权封装数据重排控制索引生成处理器，方法，系统和指令公开(公告)号：US20130283018A1
公开(公告)日：2013-10-24
申请号：US13977217
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving a packed data rearrangement control indexes generation instruction. The packed data rearrangement control indexes generation instruction indicates a destination storage location. A result is stored in the destination storage location in response to the packed data rearrangement control indexes generation instruction. The result includes a sequence of at least four non-negative integers representing packed data rearrangement control indexes. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收打包数据重排控制索引生成指令。 打包数据重排控制索引生成指令表示目的地存储位置。 响应于打包数据重排控制索引生成指令，将结果存储在目的地存储位置中。 结果包括代表压缩数据重排控制指标的至少四个非负整数的序列。 在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。 公开了其它方法，装置，系统和指令。
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6.发明申请Packed Data Rearrangement Control Indexes Precursors Generation Processors, Methods, Systems, and Instructions 有权封装数据重排控制索引前驱生成处理器，方法，系统和说明公开(公告)号：US20130275729A1
公开(公告)日：2013-10-17
申请号：US13977356
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括结果，包括至少四个非负整数的序列。 在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。 公开了其它方法，装置，系统和指令。
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7.发明授权公开(公告)号：US09904547B2
公开(公告)日：2018-02-27
申请号：US13977217
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving a packed data rearrangement control indexes generation instruction. The packed data rearrangement control indexes generation instruction indicates a destination storage location. A result is stored in the destination storage location in response to the packed data rearrangement control indexes generation instruction. The result includes a sequence of at least four non-negative integers representing packed data rearrangement control indexes. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
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8.发明申请PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF INTEGERS IN NUMERICAL ORDER THAT DIFFER BY A CONSTANT STRIDE 审中-公开处理器，方法，系统和指令，用于生成恒定序列的数字序列中的整数序列公开(公告)号：US20130283019A1
公开(公告)日：2013-10-24
申请号：US13977349
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four non-negative integers in numerical order with all integers in consecutive positions differing by a constant stride of at least two. In an aspect, storing the result including the sequence of the at least four integers is performed without calculating the at least four integers using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括以数字顺序的至少四个非负整数的序列，其中连续位置中的所有整数与至少两个的恒定步幅相差。 在一方面，使用前一条指令的结果，在不计算至少四个整数的情况下执行存储包括至少四个整数的序列的结果。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US09658850B2
公开(公告)日：2017-05-23
申请号：US13976993
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
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公开(公告)号：US09619236B2
公开(公告)日：2017-04-11
申请号：US13976992
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3013 , G06F9/30167 , G06F9/3802
摘要： An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.
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