公开(公告)号：US08971326B2

公开(公告)日：2015-03-03

申请号：US12939508

申请日：2010-11-04

申请人： Shane P. Lansing ,  Heratch Avakian

发明人： Shane P. Lansing ,  Heratch Avakian

IPC分类号： H04L12/28 ,  H04L29/06

CPC分类号： H04L69/04 ,  H04L69/22

摘要： The present invention provides methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS vile verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header. The data packet, including the suppressed packet header and suppression index are then transmitted. Once received, a payload header suppress circuit on the receiver end examines the payload header suppression index to determine if the payload header has been suppressed. For each suppressed payload header, each bit in the payload header is compared to a payload header suppression mask to determine if the bit has been suppressed. Next, for each suppressed bit, a byte string is retrieved from a payload header suppression rule and inserted into the suppressed payload header.

摘要翻译： 本发明提供了用于在硬件中执行有效载荷报头抑制（PHS），扩展和验证的方法。 PHS验证电路读取数据包直到到达第一个字节必须与PHS规则验证字节进行比较的位置。 接下来，将有效载荷报头中的所有相关字节与从有效负载报头抑制规则掩码获得的PHS虚拟验证字节进行比较。 在比较结束时，向PHS抑制电路产生指示验证已经通过或失败的标志。 对于通过验证过程的有效负载报头，有效负载报头抑制电路检查有效负载报头抑制掩码，以识别要对其进行抑制的相关字节串的有效负载报头中的一个或多个位。 接下来，抑制每个识别的比特的相关联的字节串，以产生抑制的分组有效载荷头部。 最后，将有效负载报头抑制索引添加到抑制分组有效载荷头部。 然后发送包括抑制分组报头和抑制索引的数据分组。 一旦接收到，接收机端的有效负载报头抑制电路检查有效载荷报头抑制索引，以确定有效载荷报头是否被抑制。 对于每个被抑制的有效负载报头，有效负载报头中的每个比特与有效负载报头抑制掩码进行比较，以确定该位是否被抑制。 接下来，对于每个抑制比特，从有效载荷报头抑制规则检索字节串，并插入到被抑制的有效载荷头部。

公开(公告)号：US07835360B2

公开(公告)日：2010-11-16

申请号：US11889984

申请日：2007-08-17

申请人： Shane P. Lansing ,  Heratch Avakian

发明人： Shane P. Lansing ,  Heratch Avakian

IPC分类号： H04L12/56

CPC分类号： H04L69/04 ,  H04L69/22

摘要： The present invention provides methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header. The data packet, including the suppressed packet header and suppression index are then transmitted. Once received, a payload header suppress circuit on the receiver end examines the payload header suppression index to determine if the payload header has been suppressed. For each suppressed payload header, each bit in the payload header is compared to a payload header suppression mask to determine if the bit has been suppressed. Next, for each suppressed bit, a byte string is retrieved from a payload header suppression rule and inserted into the suppressed payload header.

摘要翻译： 本发明提供了用于在硬件中执行有效载荷报头抑制（PHS），扩展和验证的方法。 PHS验证电路读取数据包直到到达第一个字节必须与PHS规则验证字节进行比较的位置。 接下来，将有效载荷报头中的所有相关字节与从有效载荷报头抑制规则掩码获得的PHS规则验证字节进行比较。 在比较结束时，向PHS抑制电路产生指示验证已经通过或失败的标志。 对于通过验证过程的有效负载报头，有效负载报头抑制电路检查有效负载报头抑制掩码，以识别要对其进行抑制的相关字节串的有效负载报头中的一个或多个位。 接下来，抑制每个识别的比特的相关联的字节串，以产生抑制的分组有效载荷头部。 最后，将有效负载报头抑制索引添加到抑制分组有效载荷头部。 然后发送包括抑制分组报头和抑制索引的数据分组。 一旦接收到，接收机端的有效负载报头抑制电路检查有效载荷报头抑制索引，以确定有效载荷报头是否被抑制。 对于每个被抑制的有效负载报头，有效负载报头中的每个比特与有效负载报头抑制掩码进行比较，以确定该位是否被抑制。 接下来，对于每个抑制比特，从有效载荷报头抑制规则检索字节串，并插入到被抑制的有效载荷头部。

公开(公告)号：US20110103385A1

公开(公告)日：2011-05-05

申请号：US12939508

申请日：2010-11-04

申请人： Shane P. Lansing ,  Heratch Avakian

发明人： Shane P. Lansing ,  Heratch Avakian

IPC分类号： H04L12/56

CPC分类号： H04L69/04 ,  H04L69/22

摘要： The present invention provides methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS vile verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header. The data packet, including the suppressed packet header and suppression index are then transmitted. Once received, a payload header suppress circuit on the receiver end examines the payload header suppression index to determine if the payload header has been suppressed. For each suppressed payload header, each bit in the payload header is compared to a payload header suppression mask to determine if the bit has been suppressed. Next, for each suppressed bit, a byte string is retrieved from a payload header suppression rule and inserted into the suppressed payload header.

摘要翻译： 本发明提供了用于在硬件中执行有效载荷报头抑制（PHS），扩展和验证的方法。 PHS验证电路读取数据包直到到达第一个字节必须与PHS规则验证字节进行比较的位置。 接下来，将有效载荷报头中的所有相关字节与从有效负载报头抑制规则掩码获得的PHS虚拟验证字节进行比较。 在比较结束时，向PHS抑制电路产生指示验证已经通过或失败的标志。 对于通过验证过程的有效负载报头，有效负载报头抑制电路检查有效负载报头抑制掩码，以识别要对其进行抑制的相关字节串的有效负载报头中的一个或多个位。 接下来，抑制每个识别的比特的相关联的字节串，以产生抑制的分组有效载荷头部。 最后，将有效负载报头抑制索引添加到抑制分组有效载荷头部。 然后发送包括抑制分组报头和抑制索引的数据分组。 一旦接收到，接收机端的有效负载报头抑制电路检查有效载荷报头抑制索引，以确定有效载荷报头是否被抑制。 对于每个被抑制的有效负载报头，有效负载报头中的每个比特与有效负载报头抑制掩码进行比较，以确定该位是否被抑制。 接下来，对于每个抑制比特，从有效载荷报头抑制规则检索字节串，并插入到被抑制的有效载荷头部。

公开(公告)号：US07738460B2

公开(公告)日：2010-06-15

申请号：US11892011

申请日：2007-08-17

申请人： Shane P. Lansing ,  Heratch Avakian

发明人： Shane P. Lansing ,  Heratch Avakian

IPC分类号： H04L12/28

CPC分类号： H04N21/42676 ,  H04L69/12 ,  H04L69/22 ,  H04L69/324 ,  H04N7/17318 ,  H04N21/437

摘要： A media access controller (MAC) is configured with a header creator circuit. The header creator circuit is configured with logic for receiving a data packet and determining whether the received data packet has an existing packet header prepended thereto. The header creator circuit is further configured to determine if the length of the received data packet includes a cyclic redundancy code. Still further, the header creator circuit is configured to determine a packet header length field value for the received data packet. If the header creator circuit determines that a cyclic redundancy code needs to be included with the received data packet, then the header creator circuit is able to generate a CRC flag. If the data packet needs to be encrypted, then the header creator circuit will generate an encryption flag if it is determined that the received data packet should be encrypted. Finally, the header creator circuit generates a packet header having a plurality of fields.

摘要翻译： 媒体接入控制器（MAC）配置有报头创建器电路。 标题创建器电路配置有用于接收数据分组并且确定接收的数据分组是否具有前面的现有分组标题的逻辑。 标题创建器电路还被配置为确定所接收的数据分组的长度是否包括循环冗余码。 另外，标题创建器电路被配置为确定所接收的数据分组的分组报头长度字段值。 如果报头创建器电路确定需要在接收的数据分组中包含循环冗余码，则报头创建器电路能够产生CRC标志。 如果数据包需要被加密，则如果确定接收的数据包应被加密，则标题创建器电路将产生加密标志。 最后，报头创建器电路产生具有多个字段的分组报头。

公开(公告)号：US07599369B2

公开(公告)日：2009-10-06

申请号：US10218582

申请日：2002-08-15

申请人： Shane Lansing ,  Heratch Avakian

发明人： Shane Lansing ,  Heratch Avakian

IPC分类号： H04L12/56

CPC分类号： H04L69/04 ,  H04L69/22

摘要： The present invention provides apparatus and methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, one or more bits are suppressed in the payload header and a the payload header suppressed and a payload header suppression index is added to the suppressed packet payload header. Following transmission, the suppression indexed is used to identify the bits to be reinserted into the suppressed payload header.

摘要翻译： 本发明提供了用于在硬件中执行有效载荷报头抑制（PHS），扩展和验证的装置和方法。 PHS验证电路读取数据包直到到达第一个字节必须与PHS规则验证字节进行比较的位置。 接下来，将有效载荷报头中的所有相关字节与从有效载荷报头抑制规则掩码获得的PHS规则验证字节进行比较。 在比较结束时，向PHS抑制电路产生指示验证已经通过或失败的标志。 对于通过验证过程的有效载荷头部，在有效载荷报头中抑制一个或多个位，并且有效负载报头被抑制，并且有效负载报头抑制索引被添加到抑制分组有效负载报头。 在发送之后，使用抑制索引来识别要重新插入到被抑制的有效负载报头中的比特。

公开(公告)号：US20080089342A1

公开(公告)日：2008-04-17

申请号：US11892011

申请日：2007-08-17

申请人： Shane Lansing ,  Heratch Avakian

发明人： Shane Lansing ,  Heratch Avakian

IPC分类号： H04L12/28

CPC分类号： H04N21/42676 ,  H04L69/12 ,  H04L69/22 ,  H04L69/324 ,  H04N7/17318 ,  H04N21/437

摘要： A media access controller (MAC) is configured with a header creator circuit. The header creator circuit is configured with logic for receiving a data packet and determining whether the received data packet has an existing packet header prepended thereto. The header creator circuit is further configured to determine if the length of the received data packet includes a cyclic redundancy code. Still further, the header creator circuit is configured to determine a packet header length field value for the received data packet. If the header creator circuit determines that a cyclic redundancy code needs to be included with the received data packet, then the header creator circuit is able to generate a CRC flag. If the data packet needs to be encrypted, then the header creator circuit will generate an encryption flag if it is determined that the received data packet should be encrypted. Finally, the header creator circuit generates a packet header having a plurality of fields.

摘要翻译： 媒体接入控制器（MAC）配置有报头创建器电路。 标题创建器电路配置有用于接收数据分组并且确定接收到的数据分组是否具有前面的现有分组标题的逻辑。 标题创建器电路还被配置为确定所接收的数据分组的长度是否包括循环冗余码。 另外，标题创建器电路被配置为确定所接收的数据分组的分组报头长度字段值。 如果报头创建器电路确定需要在接收的数据分组中包含循环冗余码，则报头创建器电路能够产生CRC标志。 如果数据包需要被加密，则如果确定接收的数据包应被加密，则标题创建器电路将产生加密标志。 最后，报头创建器电路产生具有多个字段的分组报头。

公开(公告)号：US07586914B2

公开(公告)日：2009-09-08

申请号：US10218583

申请日：2002-08-15

申请人： Shane Lansing ,  Heratch Avakian

发明人： Shane Lansing ,  Heratch Avakian

IPC分类号： H04L12/28

CPC分类号： H04N21/42676 ,  H04L69/12 ,  H04L69/22 ,  H04L69/324 ,  H04N7/17318 ,  H04N21/437

摘要： A media access controller (MAC) is configured with a DOCSIS Header creator circuit. The DOCSIS header creator circuit is configured with logic for receiving a data packet and determining whether the received data packet has an existing packet header prepended thereto. The DOCSIS header creator circuit is further configured to determine if the length of the received data packet includes a cyclic redundancy code. Still further, the DOCSIS header creator circuit is configured to determine a packet header length field value for the received data packet. If the DOCSIS header creator circuit determines that a cyclic redundancy code needs to be included in with the received data packet, then the DOCSIS header creator circuit is able to generate a CRC flag. If the data packet needs to be encrypted, then the DOCSIS header creator circuit will generate an encryption flag if it is determined that the received data packet should be encrypted. Finally, the DOCSIS header creator circuit generates a DOCSIS packet header having a plurality of fields.

摘要翻译： 媒体访问控制器（MAC）配置有DOCSIS标题创建器电路。 DOCSIS标题创建器电路配置有用于接收数据分组并且确定接收的数据分组是否具有前面的现有分组标题的逻辑。 DOCSIS标题创建器电路还被配置为确定所接收的数据分组的长度是否包括循环冗余码。 此外，DOCSIS标题创建器电路被配置为确定所接收的数据分组的分组报头长度字段值。 如果DOCSIS标题创建器电路确定需要在接收的数据分组中包含循环冗余码，则DOCSIS标题创建器电路能够产生CRC标志。 如果需要加密数据包，则如果确定接收到的数据包应被加密，则DOCSIS标题创建器电路将产生加密标志。 最后，DOCSIS标题创建器电路产生具有多个字段的DOCSIS包头。

公开(公告)号：US20080037545A1

公开(公告)日：2008-02-14

申请号：US11889984

申请日：2007-08-17

申请人： Shane Lansing ,  Heratch Avakian

发明人： Shane Lansing ,  Heratch Avakian

IPC分类号： H04L12/56

CPC分类号： H04L69/04 ,  H04L69/22

摘要： The present invention provides methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header. The data packet, including the suppressed packet header and suppression index are then transmitted. Once received, a payload header suppress circuit on the receiver end examines the payload header suppression index to determine if the payload header has been suppressed. For each suppressed payload header, each bit in the payload header is compared to a payload header suppression mask to determine if the bit has been suppressed. Next, for each suppressed bit, a byte string is retrieved from a payload header suppression rule and inserted into the suppressed payload header.

摘要翻译： 本发明提供了用于在硬件中执行有效载荷报头抑制（PHS），扩展和验证的方法。 PHS验证电路读取数据包直到到达第一个字节必须与PHS规则验证字节进行比较的位置。 接下来，将有效载荷报头中的所有相关字节与从有效载荷报头抑制规则掩码获得的PHS规则验证字节进行比较。 在比较结束时，向PHS抑制电路产生指示验证已经通过或失败的标志。 对于通过验证过程的有效负载报头，有效负载报头抑制电路检查有效负载报头抑制掩码，以识别要对其进行抑制的相关字节串的有效负载报头中的一个或多个位。 接下来，抑制每个识别的比特的相关联的字节串，以产生抑制的分组有效载荷头部。 最后，将有效负载报头抑制索引添加到抑制分组有效载荷头部。 然后发送包括抑制分组报头和抑制索引的数据分组。 一旦接收到，接收机端的有效负载报头抑制电路检查有效载荷报头抑制索引，以确定有效载荷报头是否被抑制。 对于每个被抑制的有效负载报头，有效负载报头中的每个比特与有效负载报头抑制掩码进行比较，以确定该位是否被抑制。 接下来，对于每个抑制比特，从有效载荷报头抑制规则检索字节串，并插入到被抑制的有效载荷头部。