公开(公告)号：US08990631B1

公开(公告)日：2015-03-24

申请号：US13039616

申请日：2011-03-03

Applicant: Shankar Channabasappa

Inventor： Shankar Channabasappa

IPC: G06F11/07 ,  H04L12/26

CPC classification number: H04L12/2647 ,  H04L41/06 ,  H04L45/7457 ,  H04L69/12 ,  H04L69/40

Abstract: Approaches for a packet format for error reporting in a content addressable memory (CAM) device are disclosed. The CAM device may comprise a CAM array that includes a plurality of rows, each row including a plurality of CAM cells coupled to a match line, and an error notification circuit capable of forming a packet that indicates whether the CAM device is experiencing an error condition. If an error condition was experienced by the CAM device, the response packet may also indicate the type(s) of error that was encountered. Advantageously, information about any error condition experienced by the CAM device may be quickly ascertained by a host device in which the CAM device is incorporated.

Abstract translation: 公开了一种用于内容可寻址存储器（CAM）设备中的错误报告的分组格式的方法。 CAM设备可以包括CAM阵列，其包括多行，每行包括耦合到匹配线的多个CAM单元，以及能够形成指示CAM设备是否正在经历错误状态的分组的错误通知电路 。 如果CAM设备出现错误状况，响应包也可能指示遇到的错误类型。 有利地，可以由其中并入CAM设备的主机设备快速地确定关于CAM设备经历的任何错误状况的信息。

公开(公告)号：US08792348B1

公开(公告)日：2014-07-29

申请号：US13034570

申请日：2011-02-24

Applicant: Shankar Channabasappa

Inventor： Shankar Channabasappa

IPC: H04L1/00 ,  H04L12/26

CPC classification number: H04L43/0811 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: A receiver circuit for coupling to a serial link is disclosed. The receiver circuit comprises a data buffer and serial interface circuitry. The serial interface circuitry receives serialized packet words and processes the serial words for input to the data buffer. The serial interface circuitry includes word detection logic to detect predefined control words and discard logic to selectively inhibit forwarding of one or more of the predefined control words to the data buffer.

Abstract translation: 公开了一种用于耦合到串行链路的接收机电路。 接收器电路包括数据缓冲器和串行接口电路。 串行接口电路接收串行化的分组字，并处理串行字以输入到数据缓冲器。 串行接口电路包括用于检测预定义的控制字的字检测逻辑，并且丢弃逻辑以选择性地禁止将一个或多个预定义的控制字转发到数据缓冲器。

公开(公告)号：US06349331B1

公开(公告)日：2002-02-19

申请号：US09092389

申请日：1998-06-05

Applicant: Sateesh Andra ,  Shankar Channabasappa

Inventor： Sateesh Andra ,  Shankar Channabasappa

IPC: G06F1516

CPC classification number: H04L12/40032 ,  H04L12/40136 ,  H04L12/40163 ,  H04L12/413

Abstract: A multiple channel communication system includes a plurality of network communication ports, a plurality of communication devices and an autonegotiation controller. Each communication device is coupled to a respective one of the plurality of network communication ports. The autonegotiation controller is coupled to and shared by the plurality of communication devices.

Abstract translation: 多通道通信系统包括多个网络通信端口，多个通信设备和自动协商控制器。 每个通信设备耦合到多个网络通信端口中的相应一个。 自动协商控制器耦合到多个通信设备并由多个通信设备共享。

公开(公告)号：US09178692B1

公开(公告)日：2015-11-03

申请号：US13034441

申请日：2011-02-24

Applicant: Shankar Channabasappa

Inventor： Shankar Channabasappa

IPC: H04L12/28 ,  H04L7/04 ,  H04L7/00

CPC classification number: H04L69/324 ,  H04L7/0083 ,  H04L7/041

Abstract: A method is disclosed for handling packet data. The method includes assembling request packets for transmission along a plurality of serial lanes. For each lane, at least a portion of the request packets are framed into a request link frame having a plurality of words. The request link frame is defined by a preset word length. Request training words are inserted into the request link frame at intervals corresponding to the preset word length. Response packets are queued, where the response packets include response training words having an associated latency based on the programmed interval of the request training words.

Abstract translation: 公开了一种处理分组数据的方法。 该方法包括组合要沿多个串行通道传输的请求分组。 对于每个通道，请求分组的至少一部分被框架成具有多个单词的请求链接帧。 请求链接帧由预设的字长定义。 请求训练词以对应于预设字长的间隔插入到请求链接帧中。 响应分组排队，其中响应分组包括基于请求训练词的编程间隔的具有相关等待时间的响应训练词。

公开(公告)号：US08848526B1

公开(公告)日：2014-09-30

申请号：US13034497

申请日：2011-02-24

Applicant: Shankar Channabasappa ,  Amit Arora

Inventor： Shankar Channabasappa ,  Amit Arora

IPC: H04L1/00

CPC classification number: H04L12/6418

Abstract: An integrated circuit is disclosed. The integrated circuit includes a receive port interface to receive request data at a first data rate from a first host and a transmit port interface. The transmit port interface to transmit response data words across plural serial lanes to a second host at a second data rate. The second data rate is less than a predefined line rate of symbol transfers across the plural serial lanes. The transmit port interface includes shaping logic to transmit a data word stream at the second data rate and selectively insert idle words into the data word stream such that the data words and the idle words are together transferred at the predefined line rate.

Abstract translation: 公开了一种集成电路。 集成电路包括接收端口接口，用于以第一数据速率从第一主机和发送端口接口接收请求数据。 发送端口接口，用于以多个串行通道将响应数据字以第二数据速率发送到第二主机。 第二数据速率小于跨多个串行通道的符号传输的预定线路速率。 发送端口接口包括用于以第二数据速率发送数据字流的成形逻辑，并且有选择地将空闲字插入到数据字流中，使得数据字和空闲字一起以预定线速率传送。

公开(公告)号：US08467213B1

公开(公告)日：2013-06-18

申请号：US13069220

申请日：2011-03-22

Applicant: Shankar Channabasappa

Inventor： Shankar Channabasappa

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G06F1/3275 ,  G11C5/14 ,  G11C15/00 ,  Y02D10/13 ,  Y02D10/14

Abstract: A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.

公开(公告)号：US06883025B2

公开(公告)日：2005-04-19

申请号：US10021511

申请日：2001-12-07

Applicant: Sateesh Andra ,  Shankar Channabasappa

Inventor： Sateesh Andra ,  Shankar Channabasappa

IPC: H04L12/413 ,  G06F15/16

CPC classification number: H04L12/40032 ,  H04L12/40136 ,  H04L12/40163 ,  H04L12/413

Abstract: A multiple channel communication system includes a plurality of network communication ports, a plurality of communication devices and an autonegotiation controller. Each communication device is coupled to a respective one of the plurality of network communication ports. The autonegotiation controller is coupled to and shared by the plurality of communication devices.

Abstract translation: 多通道通信系统包括多个网络通信端口，多个通信设备和自动协商控制器。 每个通信设备耦合到多个网络通信端口中的相应一个。 自动协商控制器耦合到多个通信设备并由多个通信设备共享。