Flexible shape identification for optical proximity correction in semiconductor fabrication
    1.
    发明授权
    Flexible shape identification for optical proximity correction in semiconductor fabrication 有权
    半导体制造中光学邻近校正的灵活形状识别

    公开(公告)号:US07337424B2

    公开(公告)日:2008-02-26

    申请号:US11089723

    申请日:2005-03-24

    CPC classification number: G03F1/36

    Abstract: Transient edges are used to define shapes in an integrated circuit layout for optical proximity correction. A first variation of the shape includes a first edge, a second edge satisfying an edge transition angle condition in relation to the first edge, and one or more first transition edges connected between the first edge and the second edge. A second variation of the shape includes a third edge, a fourth edge satisfying the same edge transition angle condition in relation to the third edge, and one or more second transition edges connected between the third edge and the fourth edge. Although the first transition edges are different from the second transition edges, both the first and second variations of the shape are identified as having the same shape, thereby allowing flexibility and efficiency in the shape identification process for optical proximity correction.

    Abstract translation: 瞬态边缘用于定义用于光学邻近校正的集成电路布局中的形状。 该形状的第一变型包括第一边缘,满足相对于第一边缘的边缘过渡角状态的第二边缘以及连接在第一边缘和第二边缘之间的一个或多个第一过渡边缘。 形状的第二变型包括第三边缘,第四边缘,其相对于第三边缘满足相同的边缘过渡角状态,以及连接在第三边缘和第四边缘之间的一个或多个第二过渡边缘。 虽然第一过渡边缘与第二过渡边缘不同,但是形状的第一和第二变化都被识别为具有相同的形状,从而允许用于光学邻近校正的形状识别处理中的灵活性和效率。

    Flexible shape identification for optical proximity correction in semiconductor fabrication
    2.
    发明申请
    Flexible shape identification for optical proximity correction in semiconductor fabrication 有权
    半导体制造中光学邻近校正的灵活形状识别

    公开(公告)号:US20060236287A1

    公开(公告)日:2006-10-19

    申请号:US11089723

    申请日:2005-03-24

    CPC classification number: G03F1/36

    Abstract: Transient edges are used to define shapes in an integrated circuit layout for optical proximity correction. A first variation of the shape includes a first edge, a second edge satisfying an edge transition angle condition in relation to the first edge, and one or more first transition edges connected between the first edge and the second edge. A second variation of the shape includes a third edge, a fourth edge satisfying the same edge transition angle condition in relation to the third edge, and one or more second transition edges connected between the third edge and the fourth edge. Although the first transition edges are different from the second transition edges, both the first and second variations of the shape are identified as having the same shape, thereby allowing flexibility and efficiency in the shape identification process for optical proximity correction.

    Abstract translation: 瞬态边缘用于定义用于光学邻近校正的集成电路布局中的形状。 该形状的第一变型包括第一边缘,满足相对于第一边缘的边缘过渡角状态的第二边缘以及连接在第一边缘和第二边缘之间的一个或多个第一过渡边缘。 形状的第二变型包括第三边缘,第四边缘,其相对于第三边缘满足相同的边缘过渡角状态,以及连接在第三边缘和第四边缘之间的一个或多个第二过渡边缘。 虽然第一过渡边缘与第二过渡边缘不同,但是形状的第一和第二变化都被识别为具有相同的形状,从而允许用于光学邻近校正的形状识别处理中的灵活性和效率。

    Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication
    3.
    发明申请
    Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication 有权
    半导体制造中分辨率增强的中间布局

    公开(公告)号:US20080216047A1

    公开(公告)日:2008-09-04

    申请号:US12099663

    申请日:2008-04-08

    CPC classification number: G06F17/5068 G03F1/36

    Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.

    Abstract translation: 基于集成电路的原始非分辨率增强布局和相关联的分辨率增强布局来生成中间分辨率增强状态布局。 中间分辨率增强状态布局包括对应于原始布局的部分和与片段相关联的偏移的片段,其中偏置指示片段之间的距离和分辨率增强布局。 片段还被分配了诸如片段类型,片段位置和偏差等属性。 中间分辨率增强状态布局可以组合以产生全芯片IC的布局。 组合两个或更多个中间分辨率增强状态布局并且被局部再变换以调整与中间分辨率增强状态布局相关联的分辨率增强,并获得用于全部IC的中间分辨率增强状态布局。

    Intermediate layout for resolution enhancement in semiconductor fabrication
    4.
    发明授权
    Intermediate layout for resolution enhancement in semiconductor fabrication 有权
    用于半导体制造中分辨率增强的中间布局

    公开(公告)号:US07979811B2

    公开(公告)日:2011-07-12

    申请号:US12099663

    申请日:2008-04-08

    CPC classification number: G06F17/5068 G03F1/36

    Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.

    Abstract translation: 基于集成电路的原始非分辨率增强布局和相关联的分辨率增强布局来生成中间分辨率增强状态布局。 中间分辨率增强状态布局包括对应于原始布局的部分和与片段相关联的偏移的片段,其中偏置指示片段之间的距离和分辨率增强布局。 片段还被分配了诸如片段类型,片段位置和偏差等属性。 中间分辨率增强状态布局可以组合以产生全芯片IC的布局。 组合两个或更多个中间分辨率增强状态布局并且被局部再变换以调整与中间分辨率增强状态布局相关联的分辨率增强,并获得用于全部IC的中间分辨率增强状态布局。

    Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements
    5.
    发明申请
    Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements 审中-公开
    用于选择性,增量式,可重新配置和可重复使用的半导体制造分辨率增强的方法和装置

    公开(公告)号:US20050229130A1

    公开(公告)日:2005-10-13

    申请号:US10820260

    申请日:2004-04-07

    CPC classification number: G06F17/5068

    Abstract: An automated design for manufacturability platform for integrated physical verification and manufacturing enhancement operations. Given original layouts and one or more associated resolution-enhanced layouts, intermediate resolution-enhancement state layouts are reconstructed, and selective localized resolution-enhancement reconfigurations, modifications, and/or perturbations are introduced on any existing enhancements in order to improve manufacturability and yield.

    Abstract translation: 用于集成物理验证和制造增强操作的可制造性平台的自动设计。 给定原始布局和一个或多个相关联的分辨率增强布局,重建中间分辨率增强状态布局,并且在任何现有增强上引入选择性局部分辨率增强重新配置,修改和/或扰动,以便提高可制造性和产量。

    Intermediate layout for resolution enhancement in semiconductor fabrication
    6.
    发明授权
    Intermediate layout for resolution enhancement in semiconductor fabrication 有权
    用于半导体制造中分辨率增强的中间布局

    公开(公告)号:US07404173B2

    公开(公告)日:2008-07-22

    申请号:US11074882

    申请日:2005-03-07

    CPC classification number: G06F17/5068 G03F1/36

    Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.

    Abstract translation: 基于集成电路的原始非分辨率增强布局和相关联的分辨率增强布局来生成中间分辨率增强状态布局。 中间分辨率增强状态布局包括对应于原始布局的部分和与片段相关联的偏移的片段,其中偏置指示片段之间的距离和分辨率增强布局。 片段还被分配了诸如片段类型,片段位置和偏差等属性。 中间分辨率增强状态布局可以组合以产生全芯片IC的布局。 组合两个或更多个中间分辨率增强状态布局并且被局部再变换以调整与中间分辨率增强状态布局相关联的分辨率增强,并获得用于全部IC的中间分辨率增强状态布局。

    Intermediate layout for resolution enhancement in semiconductor fabrication
    7.
    发明申请
    Intermediate layout for resolution enhancement in semiconductor fabrication 有权
    用于半导体制造中分辨率增强的中间布局

    公开(公告)号:US20050229131A1

    公开(公告)日:2005-10-13

    申请号:US11074882

    申请日:2005-03-07

    CPC classification number: G06F17/5068 G03F1/36

    Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.

    Abstract translation: 基于集成电路的原始非分辨率增强布局和相关联的分辨率增强布局来生成中间分辨率增强状态布局。 中间分辨率增强状态布局包括对应于原始布局的部分和与片段相关联的偏移的片段,其中偏置指示片段之间的距离和分辨率增强布局。 片段还被分配了诸如片段类型,片段位置和偏差等属性。 中间分辨率增强状态布局可以组合以产生全芯片IC的布局。 组合两个或更多个中间分辨率增强状态布局并且被局部再变换以调整与中间分辨率增强状态布局相关联的分辨率增强,并获得用于全部IC的中间分辨率增强状态布局。

    Record player
    8.
    外观设计

    公开(公告)号:USD873235S1

    公开(公告)日:2020-01-21

    申请号:US29672481

    申请日:2018-12-06

    Applicant: Xin Wang

    Designer: Xin Wang

    Interactive system and method for creating music by substituting audio tracks

    公开(公告)号:US10283097B2

    公开(公告)日:2019-05-07

    申请号:US15964052

    申请日:2018-04-26

    Abstract: In order to help music players without sufficient musical knowledge to adapt original music pieces but still keep the original style, the present invention provides an interactive system and the accompanying method for creating music by substituting audio tracks. The interactive system includes a database of musical elements that comprises tonality, tempo, beat, timbre, texture, chord, and pitch, a database of music that contains multiple original music pieces, and a processor. As a result, players without strong knowledge in music theories can create adapted a music piece that matches the style of the original one.

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