公开(公告)号：US20070134854A1

公开(公告)日：2007-06-14

申请号：US11302479

申请日：2005-12-13

申请人： Shaoqiang Zhang ,  Purakh Verma ,  Sanford Chu

发明人： Shaoqiang Zhang ,  Purakh Verma ,  Sanford Chu

IPC分类号： H01L21/8232 ,  H01L21/335

CPC分类号： H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/7378

摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.

摘要翻译： 用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。 实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。 由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。 该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。 作为插件模块，与SiGe BiCMOS工艺完全集成。 高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。 自对准N +基极植入可以减少基极电阻和寄生EB电容。 极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

公开(公告)号：US08536016B2

公开(公告)日：2013-09-17

申请号：US13236295

申请日：2011-09-19

申请人： Shao-fu Sanford Chu ,  Shaoqiang Zhang ,  Johnny Kok Wai Chew

发明人： Shao-fu Sanford Chu ,  Shaoqiang Zhang ,  Johnny Kok Wai Chew

IPC分类号： H01L21/20

CPC分类号： H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.

摘要翻译： 一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且互连所述第一组金属层，包括互连与第二簇相邻的第一簇，以形成电容器。

公开(公告)号：US20140210009A1

公开(公告)日：2014-07-31

申请号：US13754065

申请日：2013-01-30

申请人： Han Xiao ,  Shaoqiang Zhang ,  Sanford Chu ,  Liming Li

发明人： Han Xiao ,  Shaoqiang Zhang ,  Sanford Chu ,  Liming Li

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region.

摘要翻译： 公开了能够承受高电压应用的FIN形状场效应晶体管（FINFET）和所得到的器件的方法。 实施例包括在衬底上形成源极和漏极，在衬底上形成薄体（FIN）并连接源极和漏极，在FIN的第一部分的顶部和侧面上形成栅极，从而限定漏极 在栅极和漏极之间的FIN的FIN边缘区域，并且在漏极侧FIN区域中在FIN的第二部分的顶表面和侧表面上形成屏蔽区域。

公开(公告)号：US07488662B2

公开(公告)日：2009-02-10

申请号：US11302479

申请日：2005-12-13

申请人： Shaoqiang Zhang ,  Purakh Raj Verma ,  Sanford Chu

发明人： Shaoqiang Zhang ,  Purakh Raj Verma ,  Sanford Chu

IPC分类号： H01L21/331

CPC分类号： H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/7378

摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.

摘要翻译： 用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。 实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。 由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。 该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。 作为插件模块，与SiGe BiCMOS工艺完全集成。 高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。 自对准N +基极植入可以减少基极电阻和寄生EB电容。 极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

公开(公告)号：US07846805B2

公开(公告)日：2010-12-07

申请号：US12368283

申请日：2009-02-09

申请人： Shaoqiang Zhang ,  Purakh Raj Verma ,  Sanford Chu

发明人： Shaoqiang Zhang ,  Purakh Raj Verma ,  Sanford Chu

IPC分类号： H01L21/331

CPC分类号： H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/7378

摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.

摘要翻译： 用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。 实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。 由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。 该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。 作为插件模块，与SiGe BiCMOS工艺完全集成。 高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。 自对准N +基极植入可以减少基极电阻和寄生EB电容。 极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

公开(公告)号：US09006055B2

公开(公告)日：2015-04-14

申请号：US13754065

申请日：2013-01-30

申请人： Han Xiao ,  Shaoqiang Zhang ,  Sanford Chu ,  Liming Li

发明人： Han Xiao ,  Shaoqiang Zhang ,  Sanford Chu ,  Liming Li

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region.

摘要翻译： 公开了能够承受高电压应用的FIN形状场效应晶体管（FINFET）和所得到的器件的方法。 实施例包括在衬底上形成源极和漏极，在衬底上形成薄体（FIN）并连接源极和漏极，在FIN的第一部分的顶部和侧面上形成栅极，由此限定漏极 在栅极和漏极之间的FIN的FIN边缘区域，并且在漏极侧FIN区域中在FIN的第二部分的顶表面和侧表面上形成屏蔽区域。

公开(公告)号：US20120007214A1

公开(公告)日：2012-01-12

申请号：US13236295

申请日：2011-09-19

申请人： Shao-fu Sanford Chu ,  Shaoqiang Zhang ,  Johnny Kok Wai Chew

发明人： Shao-fu Sanford Chu ,  Shaoqiang Zhang ,  Johnny Kok Wai Chew

IPC分类号： H01L29/92 ,  H01L21/20

CPC分类号： H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.

摘要翻译： 一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且互连所述第一组金属层，包括互连与第二簇相邻的第一簇，以形成电容器。