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1.发明授权Methods and apparatus for decoding images using dedicated hardware circuitry and a programmable processor 失效使用专用硬件电路和可编程处理器对图像进行解码的方法和装置公开(公告)号：US06829303B1
公开(公告)日：2004-12-07
申请号：US09442363
申请日：1999-11-17
IPC分类号： H04N712
CPC分类号： H04N19/423 , H04N19/43 , H04N19/44 , H04N19/61
摘要： Video decoder methods and apparatus are described. In accordance with the invention, hardware decoder circuitry, e.g., intra-coded image decoding circuitry and motion vector reconstruction circuitry, is used in combination with a general purpose processor, e.g., Pentium processor, to perform video decoding operations. The video decoder hardware circuitry of the present invention is responsible for performing non-memory intensive functions. The general purpose processor or a general purpose processor operating in conjunction with a graphics processor are used to perform memory intensive video decoding operations such as motion compensated predictions. The video decoding hardware circuitry of the present invention can be implemented as a separate physical device, e.g., chip, or can be implemented on the same physical chip as a general purpose processor with which it works. By using the video decoding hardware circuitry of the present invention in combination with a CPU, a computer system's ability to perform video decoding operations can be significantly increased at little cost in terms of additional hardware.
摘要翻译： 描述视频解码器方法和装置。 根据本发明，硬件解码器电路，例如帧内编码图像解码电路和运动矢量重构电路，与通用处理器（例如奔腾处理器）结合使用，以执行视频解码操作。 本发明的视频解码器硬件电路负责执行非存储器密集型功能。 与图形处理器结合操作的通用处理器或通用处理器用于执行存储密集型视频解码操作，例如运动补偿预测。 本发明的视频解码硬件电路可以被实现为单独的物理设备，例如芯片，或者可以在与其工作的通用处理器相同的物理芯片上实现。 通过使用本发明的视频解码硬件电路与CPU的组合，计算机系统的执行视频解码操作的能力可以在额外的硬件方面以很小的成本显着增加。
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2.发明授权Registers and methods for accessing registers for use in a single instruction multiple data system 失效访问寄存器的寄存器和方法用于单指令多数据系统公开(公告)号：US06175892B1
公开(公告)日：2001-01-16
申请号：US09099989
申请日：1998-06-19
IPC分类号： G06F1200
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/30141 , G11C7/1006
摘要： Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registers and register arrays of the present invention may be used when implementing a system based on a SIMD architecture. Registers implemented in accordance with the present invention include a plurality of pass gates that allow an entire n-bit word stored in the register to be accessed and output as a single word or for a sub-word portion of a stored word to be accessed and output. During standard operation the registers are accessed on a word basis. However, during column access operations, e.g., when performing a transpose operation, access is performed on a sub-word basis. The ability to access the registers of the present invention on a word or sub-word level make implementing transpose and various other row/column data manipulation operations possible in a relatively straightforward manner without data buffering. In addition to the novel registers and register arrays of the present invention, various aspects of the present invention are directed to new and novel SIMD instructions, e.g., SIMD move, add, and move instructions, which support the specification of data to be processed as operands which identify rows or columns of register arrays as opposed to merely identifying registers as done with conventional commands. A transpose command is also supported.
摘要翻译： 描述了实现单指令多数据（SIMD）信号处理操作的方法和装置。 本发明的装置包括新的寄存器和寄存器阵列，其允许以字以及子字或子寄存器级别访问数据。 当基于SIMD架构实现系统时，可以使用本发明的寄存器和寄存器阵列。 根据本发明实现的寄存器包括多个通过门，其允许存储在寄存器中的整个n位字被访问并输出为单个字或要存储的字的子字部分被访问， 输出。 在标准操作期间，寄存器是以字为单位访问的。 然而，在列访问操作期间，例如，当执行转置操作时，以子字为基础执行访问。 在字或子字级别访问本发明的寄存器的能力使得实现转置和各种其他行/列数据操纵操作可以以相对直接的方式进行，而不需要数据缓冲。 除了本发明的新型寄存器和寄存器阵列之外，本发明的各个方面涉及新的和新颖的SIMD指令，例如SIMD移动，添加和移动指令，其支持要处理的数据的规范为 识别寄存器阵列的行或列的操作数，而不是像传统命令一样完成标识寄存器。 还支持转置命令。
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公开(公告)号：US06529930B1
公开(公告)日：2003-03-04
申请号：US09393591
申请日：1999-09-09
IPC分类号： G06F9302
CPC分类号： G06F7/48 , G06F7/49921
摘要： Methods and apparatus for performing signed saturation of binary numbers to arbitrary powers of two are described. Given an n-bit signed binary word, the methods and apparatus of the present invention perform a signed saturation to k-bits where the value of k can vary such that 1
摘要翻译： 描述了对二进制数进行符号饱和的任意幂的方法和装置。 给定一个n位有符号的二进制字，本发明的方法和装置对k位进行符号饱和，其中k的值可以变化使得1
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公开(公告)号：US06621867B1
公开(公告)日：2003-09-16
申请号：US09390274
申请日：1999-09-07
IPC分类号： H04N712
CPC分类号： H04N5/142 , G06T7/12 , G06T2207/10016 , G06T2207/20052
摘要： Edge detection methods and apparatus which utilize the dc dct differential data included in encoded images, e.g., an MPEG-2 encoded video stream, are described. Use of the dc dct differential data allows efficient methods for detecting the presence of edges within encoded images. The edge detection methods and apparatus of the present invention can be used where differential coding of the DC DCT coefficients is employed. Accordingly, the edge detection methods of the present invention are applicable to MPEG-2 encoded images as well as other differentially encoded images.
摘要翻译： 描述利用包括在编码图像中的直流dct差分数据（例如MPEG-2编码视频流）的边缘检测方法和装置。 使用直流差分数据可以有效地检测编码图像中边缘的存在。 在采用DC DCT系数的差分编码的情况下，可以使用本发明的边缘检测方法和装置。 因此，本发明的边缘检测方法可应用于MPEG-2编码图像以及其它差分编码图像。
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5.发明授权公开(公告)号：US06397237B1
公开(公告)日：2002-05-28
申请号：US09809594
申请日：2001-03-15
IPC分类号： G06F738
CPC分类号： G06F9/30094 , G06F7/48 , G06F7/49994 , G06F2207/3828 , H04N19/61
摘要： Methods and apparatus for implementing and using a sign(x) function are described. In accordance with the present invention, the sign(x) function is implemented in hardware, e.g., by incorporating a simple circuit of the present invention into a central processing unit (CPU). By taking a hardware approach as opposed to the known software approach to implementing a sign(x) function, the present invention provides for an efficient sign(x) function implementation that is well suited for both SISD and SIMD systems. The hardware required to implement the sign(x) function in accordance with the present invention is relatively simple and allows for the sign(x) function to be determined in a single processor clock cycle. This is in sharp contrast to the plurality of processor clock cycles normally required to determine the sign(x) function in software embodiments. A processor sign(x) command is supported in embodiments where the hardware for performing the sign(x) function is incorporated into a processor. By incorporating a single sign(x) circuit into a processor a SISD sign(x) function can be supported. By duplicating the basic sign(x) hardware within a processor, in accordance with the present invention, a SIMD sign(x) function can be implemented. The sign(x) hardware and novel sign(x) processor command of the present invention, can be used to facilitate a variety of applications where the sign(x) function is encountered.
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公开(公告)号：US06292814B1
公开(公告)日：2001-09-18
申请号：US09105225
申请日：1998-06-26
IPC分类号： G06F700
CPC分类号： G06F9/30094 , G06F7/48 , G06F7/49994 , G06F2207/3828 , H04N19/61
摘要： Methods and apparatus for implementing and using a sign(x) function are described. In accordance with the present invention, the sign(x) function is implemented in hardware, e.g., by incorporating a simple circuit of the present invention into a central processing unit (CPU). By taking a hardware approach as opposed to the known software approach to implementing a sign(x) function, the present invention provides for an efficient sign(x) function implementation that is well suited for both SISD and SIMD systems. The hardware required to implement the sign(x) function in accordance with the present invention is relatively simple and allows for the sign(x) function to be determined in a single processor clock cycle. This is in sharp contrast to the plurality of processor clock cycles normally required to determine the sign(x) function in software embodiments. A processor sign(x) command is supported in embodiments where the hardware for performing the sign(x) function is incorporated into a processor. By incorporating a single sign(x) circuit into a processor a SISD sign(x) function can be supported. By duplicating the basic sign(x) hardware within a processor, in accordance with the present invention, a SIMD sign(x) function can be implemented. The sign(x) hardware and novel sign(x) processor command of the present invention, can be used to facilitate a variety of applications where the sign(x) function is encountered.
摘要翻译： 描述了用于实现和使用sign（x）功能的方法和装置。 根据本发明，例如通过将本发明的简单电路结合到中央处理单元（CPU）中，符号（x）功能是以硬件实现的。 通过采用硬件方法而不是实现符号（x）功能的已知软件方法，本发明提供了非常适合于SISD和SIMD系统的有效符号（x）功能实现。 根据本发明实现符号（x）功能所需的硬件相对简单，并允许在单个处理器时钟周期中确定符号（x）功能。 这与在软件实施例中确定符号（x）功能通常需要的多个处理器时钟周期形成鲜明对比。 在用于执行符号（x）功能的硬件被并入处理器的实施例中，支持处理器符号（x）命令。 通过将单符号（x）电路并入处理器，可以支持SISD符号（x）功能。 通过在处理器内复制基本符号（x）硬件，根据本发明，可以实现SIMD符号（x）功能。 本发明的符号（x）硬件和新颖的（x）处理器命令可以用于促进遇到符号（x）功能的各种应用。
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