利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

4 条记录 (耗时 0.01 秒)

    Decision feedback equalizers and methods of decision feedback equalization
    1.
    发明授权
    Decision feedback equalizers and methods of decision feedback equalization 有权

    公开(公告)号：US10187234B1

    公开(公告)日：2019-01-22

    申请号：US15810240

    申请日：2017-11-13

    申请人： Shayan Shahramian ,  Behzad Dehlaghi

    发明人： Shayan Shahramian ,  Behzad Dehlaghi

    IPC分类号： H04L27/01 ,  H04B1/12 ,  H04L25/03

    摘要： The present disclosure relates to a 1/K-rate decision feedback equalizer (DFE) and to a decision feedback equalization method. The DFE comprises: (i) a summing circuit configured to combine K intersymbol interference (ISI) cancellation signals with an input signal of the DFE, (ii) K branches each including a reset-to-zero (RZ) latch configured to receive an output signal of the summing circuit according to a clock signal and to produce a RZ signal, and (iii) a feedback circuit including K filters each configured to receive a respective RZ signal from a respective RZ latch and to produce a respective ISI cancellation signal. The method comprises: (i) producing an output signal for K branches based on K cancellation signals and on an input signal, (ii) producing K RZ signals based on the output signal and on a clock signal, and (iii) producing the K ISI cancellation signals based on the K RZ signals.

    Receiver recovering a signal clock from a received data signal, and a clock recovery method implemented in the receiver
    3.
    发明授权
    Receiver recovering a signal clock from a received data signal, and a clock recovery method implemented in the receiver 有权

    公开(公告)号：US10135604B1

    公开(公告)日：2018-11-20

    申请号：US15809065

    申请日：2017-11-10

    申请人： Behzad Dehlaghi ,  Shayan Shahramian

    发明人： Behzad Dehlaghi ,  Shayan Shahramian

    IPC分类号： H04L7/033

    摘要： The present disclosure relates to a receiver and to a method implemented in the receiver for recovering a signal clock from a received data signal. Successive edge transitions between successive data samples of the received data signal are detected according to a clock recovered in the receiver. The recovered clock is adjusted based on a combination of weights assigned to at least some edge transitions among the plurality of successive edge transitions. In particular, (i) each very early transition is assigned a first weight having a first sign, (ii) each early transition is assigned a second weight having the first sign, (iii) each late transition is assigned a third weight having a second sign opposite from the first sign, and (iv) each very late transition is assigned a fourth weight having the second sign.