公开(公告)号：US20070170269A1

公开(公告)日：2007-07-26

申请号：US11649370

申请日：2007-01-04

申请人： Sheldon Woodhouse ,  Richard Grisenthwaite ,  Daryl Bradley ,  Edmond Ashfield

发明人： Sheldon Woodhouse ,  Richard Grisenthwaite ,  Daryl Bradley ,  Edmond Ashfield

IPC分类号： G06K19/06

CPC分类号： G06F13/4265

摘要： Within an integrated circuit 2 independently controllable domains 4, 6, 8, 10, 12, 14 may be unable to complete pending transactions taking place between domains. Each domain is provided with a state machine 20, 22 which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not communicating triggers modified behaviour. This can provide that the predetermined transaction protocol is not broken and/or complete a partially completed transaction when the domain concerned has recovered from an error or other event which disrupted the communication.

摘要翻译： 在集成电路2内，可独立控制的域4,6,8,10,12,14可能无法完成域之间发生的待处理事务。 每个域被提供有状态机20,22，该状态机响应于另一个域内的状态机的状态，并且当这指示另一个域不通信触发修改的行为时。 这可以规定，当有关的域已经从错误或其他中断通信的事件中恢复时，预定的事务协议不被破坏和/或完成部分完成的事务。

公开(公告)号：US20060049264A1

公开(公告)日：2006-03-09

申请号：US11045580

申请日：2005-01-31

申请人： Daryl Bradley ,  Richard Grisenthwaite ,  Sheldon Woodhouse

发明人： Daryl Bradley ,  Richard Grisenthwaite ,  Sheldon Woodhouse

IPC分类号： G06K19/06

CPC分类号： G06F13/4265

摘要： Within an integrated circuit 2 independently controllable domains 4, 6, 8, 10, 12, 14 may be unable to complete pending transactions taking place between domains. Each domain is provided with a transaction level state machine 20, 22 which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not capable of communicating triggers default behaviour ensuring that the predetermined transaction protocol is not broken.

摘要翻译： 在集成电路2内，可独立控制的域4,6,8,10,12,14可能无法完成域之间发生的待处理事务。 每个域被提供有事务级状态机20,22，其响应于另一域内的状态机的状态，并且当这指示另一个域不能传送触发默认行为时，确保预定的事务协议是 不破

公开(公告)号：US20070255974A1

公开(公告)日：2007-11-01

申请号：US11414551

申请日：2006-05-01

申请人： David Gilday ,  Daryl Bradley ,  Edmond Ashfield

发明人： David Gilday ,  Daryl Bradley ,  Edmond Ashfield

IPC分类号： G06F1/04

CPC分类号： G06F1/10 ,  H03K23/52

摘要： A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock. Furthermore the clock-signal comparator is implemented in a hardware description language and integrated in a simulation of the operation of a data processing apparatus to detect timing errors that arise from numerical artefacts of the simulation as well as timing errors that arise from configuration and layout of the circuit elements of the data processing apparatus being simulated.

摘要翻译： 提供一种数据处理系统，其具有时钟信号比较器，该时钟信号比较器包括用于接收参考时钟信号的参考输入端口和用于接收相应另外的时钟信号的至少另一输入端口。 在时钟信号比较器内提供校验逻辑，以在预定时间窗内检查参考时钟信号的时钟沿与另一时钟信号的对应时钟沿之间的对应关系。 检查逻辑可操作以在数据处理系统的操作期间检查对应关系。 时钟信号比较器可以被提供在集成电路上或作为数据处理装置的一部分，该数据处理装置具有至少两个不同的定时域，例如与相同时钟的两个不同实例相关联的定时域。 此外，时钟信号比较器以硬件描述语言实现，并且集成在数据处理装置的操作的仿真中，以检测由仿真的数字伪像产生的定时误差以及由配置和布局引起的定时误差 模拟数据处理装置的电路元件。

公开(公告)号：US20050039078A1

公开(公告)日：2005-02-17

申请号：US10715394

申请日：2003-11-19

申请人： Daryl Bradley ,  Sheldon Woodhouse ,  Andrew Swaine

发明人： Daryl Bradley ,  Sheldon Woodhouse ,  Andrew Swaine

IPC分类号： G06F11/28 ,  G06F11/34 ,  H03K19/003

CPC分类号： G06F11/348 ,  G06F11/3476

摘要： A trace data formatter 30 assembles trace data frames 50. These trace data frames 50 include bytes which may either serve to carry a trace data source identifier ID or trace data. A system being traced has multiple trace data sources 12, 14, 16, 18 and when the trace data source which is generating the current trace data stream changes then a trace data source identifier ID is inserted within the trace data stream.

摘要翻译： 跟踪数据格式器30组装跟踪数据帧50.这些跟踪数据帧50包括可用于携带跟踪数据源标识符ID或跟踪数据的字节。 正在跟踪的系统具有多个跟踪数据源12,14,16,18，并且当生成当前跟踪数据流的跟踪数据源改变时，跟踪数据源标识符ID被插入跟踪数据流内。

公开(公告)号：US20050210447A1

公开(公告)日：2005-09-22

申请号：US10801137

申请日：2004-03-16

申请人： Daryl Bradley ,  Andrew Swaine ,  Sheldon Woodhouse ,  John Horley

发明人： Daryl Bradley ,  Andrew Swaine ,  Sheldon Woodhouse ,  John Horley

IPC分类号： G06F9/44

CPC分类号： G06F11/3476

摘要： A trace data system is provided in which flush request signals are generated and passed to trace data sources to trigger them to output any buffered trace data they are storing which was generated prior to the flush request being signalled. When the trace data has been flushed from these trace data sources, they signal this by generating a flush complete signal. The flushing of trace data may advantageously be performed prior to a power-down operation and using a trace bus bridge.

摘要翻译： 提供跟踪数据系统，其中生成刷新请求信号并将其传递到跟踪数据源，以触发它们输出它们正在存储的任何缓冲的跟踪数据，该数据是在发送刷新请求之前生成的。 当跟踪数据从这些跟踪数据源中刷新时，它们会通过生成一个完整的完成信号来发出信号。 跟踪数据的刷新可以有利地在掉电操作之前和使用跟踪总线桥处执行。

公开(公告)号：US20050034026A1

公开(公告)日：2005-02-10

申请号：US10635920

申请日：2003-08-07

申请人： Andrew Swaine ,  Daryl Bradley ,  Sheldon Woodhouse

发明人： Andrew Swaine ,  Daryl Bradley ,  Sheldon Woodhouse

IPC分类号： G06F11/28 ,  G06F11/34 ,  H03K19/003

CPC分类号： G06F11/348 ,  G06F11/3476

摘要： An integrated circuit 2 is provided with multiple sources 12, 14, 16, 18 of trace data streams that are input via respective dedicated trace buses 20, 24 to a trace data stream combiner 22, 26. The trace data bus has trace data signal lines ATDATA for carrying trace data signals and trace source identifying signal lines ATID for carrying trace source identifying signals. A trace data stream replicator 28 may be used to replicate a single trace data stream such that the resulting multiple trace data streams may be subject to different post-replication processing/filtering as desired.

摘要翻译： 集成电路2具有通过相应的专用跟踪总线20,24输入到跟踪数据流组合器22,26的多个源12,14,16,18的跟踪数据流。跟踪数据总线具有跟踪数据信号线 ATDATA用于承载跟踪数据信号和跟踪源识别信号线ATID，用于承载跟踪源识别信号。 跟踪数据流复制器28可以用于复制单个跟踪数据流，使得所得到的多个跟踪数据流可以根据需要进行不同的后复制处理/过滤。

公开(公告)号：US20050033553A1

公开(公告)日：2005-02-10

申请号：US10635916

申请日：2003-08-07

申请人： Andrew Swaine ,  Daryl Bradley ,  Sheldon Woodhouse

发明人： Andrew Swaine ,  Daryl Bradley ,  Sheldon Woodhouse

IPC分类号： G06F11/28 ,  G04F1/00 ,  G06F11/34

CPC分类号： G06F11/3476 ,  G06F11/3636

摘要： An integrated circuit is provided with multiple data processing components associated with respective sources which generate trace data streams. A reference timestamp generator is provided and the trace data streams are annotated such that they are output off-chip together with reference timestamp data. Outputting the reference timestamp data together with the trace data streams enables temporal correlation between points in different trace data streams by trace analysis tools.

摘要翻译： 集成电路设置有与产生跟踪数据流的各个源相关联的多个数据处理组件。 提供参考时间戳生成器，并且跟踪数据流被注释，使得它们与参考时间戳数据一起离开芯片输出。 将引用时间戳数据与跟踪数据流一起输出，可以通过跟踪分析工具实现不同跟踪数据流中的点之间的时间相关性。